blob: ec8523eb95c4f5ef8db865ce4a3ee7adb4cf6ab4 [file] [log] [blame]
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +09001/*
2 * Configuation settings for the Hitachi Solution Engine 7720
3 *
4 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +09007 */
8
9#ifndef __MS7720SE_H
10#define __MS7720SE_H
11
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090012#define CONFIG_SH 1
13#define CONFIG_SH3 1
14#define CONFIG_CPU_SH7720 1
15#define CONFIG_MS7720SE 1
16
17#define CONFIG_CMD_FLASH
Mike Frysingerbdab39d2009-01-28 19:08:14 -050018#define CONFIG_CMD_SAVEENV
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090019#define CONFIG_CMD_SDRAM
20#define CONFIG_CMD_MEMORY
21#define CONFIG_CMD_CACHE
22#define CONFIG_CMD_PCMCIA
23#define CONFIG_CMD_IDE
24#define CONFIG_CMD_EXT2
25
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090026#define CONFIG_BAUDRATE 115200
27#define CONFIG_BOOTARGS "console=ttySC0,115200"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +000028#define CONFIG_BOOTFILE "/boot/zImage"
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090029#define CONFIG_LOADADDR 0x8E000000
30
31#define CONFIG_VERSION_VARIABLE
32#undef CONFIG_SHOW_BOOT_PROGRESS
33
34/* MEMORY */
35#define MS7720SE_SDRAM_BASE 0x8C000000
36#define MS7720SE_FLASH_BASE_1 0xA0000000
37#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
38
Nobuhiro Iwamatsu46198752011-01-17 21:05:35 +090039#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
42#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
43#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090044/* Buffer size for Boot Arguments passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_BARGSIZE 512
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090046/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090048
49/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020050#define CONFIG_SCIF_CONSOLE 1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090051#define CONFIG_CONS_SCIF0 1
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
54#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
57#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090058
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
60#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
61#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
62#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090064
65
66/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020068#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#undef CONFIG_SYS_FLASH_QUIET_TEST
70#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090073
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_MAX_FLASH_SECT 150
75#define CONFIG_SYS_MAX_FLASH_BANKS 1
76#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090077
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020078#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020079#define CONFIG_ENV_SECT_SIZE (64 * 1024)
80#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
82#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
83#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090084
85/* Board Clock */
86#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090087#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
88#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020089#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090090
91/* PCMCIA */
92#define CONFIG_IDE_PCMCIA 1
93#define CONFIG_MARUBUN_PCCARD 1
94#define CONFIG_PCMCIA_SLOT_A 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_IDE_MAXDEVICE 1
96#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
97#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
98#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
99#define CONFIG_SYS_MARUBUN_IO 0xb8600000
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +0900100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_PIO_MODE 1
102#define CONFIG_SYS_IDE_MAXBUS 1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +0900103#define CONFIG_DOS_PARTITION 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
105#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
106#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
107#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
108#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +0530109#define CONFIG_IDE_SWAP_IO
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +0900110
111#endif /* __MS7720SE_H */