blob: c3de9a999e952e3f893a6ae9efa2538e53b79e3e [file] [log] [blame]
Tom Warren07067142013-01-28 13:32:13 +00001/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _TEGRA114_COMMON_H_
18#define _TEGRA114_COMMON_H_
19#include "tegra-common.h"
20
Thierry Reding0d79f4f2013-07-18 12:13:40 -070021/* Cortex-A15 uses a cache line size of 64 bytes */
22#define CONFIG_SYS_CACHELINE_SIZE 64
23
Tom Warren07067142013-01-28 13:32:13 +000024/*
25 * NS16550 Configuration
26 */
27#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
33
34/* Environment information, boards can override if required */
35#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
36
37/*
38 * Miscellaneous configurable options
39 */
40#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
41#define CONFIG_STACKBASE 0x82800000 /* 40MB */
42
43/*-----------------------------------------------------------------------
44 * Physical Memory Map
45 */
46#define CONFIG_SYS_TEXT_BASE 0x8010E000
47
48/*
49 * Memory layout for where various images get loaded by boot scripts:
50 *
51 * scriptaddr can be pretty much anywhere that doesn't conflict with something
52 * else. Put it above BOOTMAPSZ to eliminate conflicts.
53 *
54 * kernel_addr_r must be within the first 128M of RAM in order for the
55 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
56 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
57 * should not overlap that area, or the kernel will have to copy itself
58 * somewhere else before decompression. Similarly, the address of any other
59 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
60 * this up to 16M allows for a sizable kernel to be decompressed below the
61 * compressed load address.
62 *
63 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
64 * the compressed kernel to be up to 16M too.
65 *
66 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
67 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
68 */
69#define MEM_LAYOUT_ENV_SETTINGS \
70 "scriptaddr=0x90000000\0" \
71 "kernel_addr_r=0x81000000\0" \
72 "fdt_addr_r=0x82000000\0" \
73 "ramdisk_addr_r=0x82100000\0"
74
75/* Defines for SPL */
76#define CONFIG_SPL_TEXT_BASE 0x80108000
77#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
78#define CONFIG_SPL_STACK 0x800ffffc
79
Tom Warrena7f8b5e2013-02-08 07:25:32 +000080/* Total I2C ports on Tegra114 */
81#define TEGRA_I2C_NUM_CONTROLLERS 5
82
Jim Lind6cf7072013-06-21 19:05:48 +080083/* For USB EHCI controller */
84#define CONFIG_EHCI_IS_TDI
85
Tom Warren07067142013-01-28 13:32:13 +000086#endif /* _TEGRA114_COMMON_H_ */