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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 2a6f0230619a821eae034c741fc20d586776b9ad / . / arch / arm / dts / imx8mm-kontron-n801x-som.dtsi
blob: 3b66e560927c9c4e2740121a1c8dacb80af1d7f8 [file] [log] [blame]
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6#include "imx8mm.dtsi"
7
8/ {
9 model = "Kontron i.MX8MM N801X SoM";
10 compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
11
12 memory@40000000 {
13 device_type = "memory";
14 /*
15 * There are multiple SoM flavors with different DDR sizes.
16 * The smallest is 1GB. For larger sizes the bootloader will
17 * update the reg property.
18 */
19 reg = <0x0 0x40000000 0 0x80000000>;
20 };
21
22 chosen {
23 stdout-path = &uart3;
24 };
25};
26
27&A53_0 {
28 cpu-supply = <&reg_vdd_arm>;
29};
30
31&A53_1 {
32 cpu-supply = <&reg_vdd_arm>;
33};
34
35&A53_2 {
36 cpu-supply = <&reg_vdd_arm>;
37};
38
39&A53_3 {
40 cpu-supply = <&reg_vdd_arm>;
41};
42
43&ddrc {
44 operating-points-v2 = <&ddrc_opp_table>;
45
46 ddrc_opp_table: opp-table {
47 compatible = "operating-points-v2";
48
49 opp-25M {
50 opp-hz = /bits/ 64 <25000000>;
51 };
52
53 opp-100M {
54 opp-hz = /bits/ 64 <100000000>;
55 };
56
57 opp-750M {
58 opp-hz = /bits/ 64 <750000000>;
59 };
60 };
61};
62
63&ecspi1 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_ecspi1>;
Frieder Schrempffecfe772022-06-14 15:03:18 +0200[diff] [blame]66 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]67 status = "okay";
68
Frieder Schrempffecfe772022-06-14 15:03:18 +0200[diff] [blame]69 flash@0 {
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]70 compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
71 spi-max-frequency = <80000000>;
72 reg = <0>;
Frieder Schrempf2a6f0232022-08-24 15:59:07 +0200[diff] [blame^]73
74 partitions {
75 compatible = "fixed-partitions";
76 #address-cells = <1>;
77 #size-cells = <1>;
78
79 partition@0 {
80 label = "u-boot";
81 reg = <0x0 0x1e0000>;
82 };
83
84 partition@1e0000 {
85 label = "env";
86 reg = <0x1e0000 0x10000>;
87 };
88
89 partition@1f0000 {
90 label = "env_redundant";
91 reg = <0x1f0000 0x10000>;
92 };
93 };
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]94 };
95};
96
97&i2c1 {
98 clock-frequency = <400000>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_i2c1>;
101 status = "okay";
102
103 pca9450: pmic@25 {
104 compatible = "nxp,pca9450a";
105 reg = <0x25>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_pmic>;
108 interrupt-parent = <&gpio1>;
109 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
110 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
111
112 regulators {
113 reg_vdd_soc: BUCK1 {
114 regulator-name = "buck1";
115 regulator-min-microvolt = <800000>;
116 regulator-max-microvolt = <850000>;
117 regulator-boot-on;
118 regulator-always-on;
119 regulator-ramp-delay = <3125>;
120 nxp,dvs-run-voltage = <850000>;
121 nxp,dvs-standby-voltage = <800000>;
122 };
123
124 reg_vdd_arm: BUCK2 {
125 regulator-name = "buck2";
126 regulator-min-microvolt = <850000>;
127 regulator-max-microvolt = <950000>;
128 regulator-boot-on;
129 regulator-always-on;
130 regulator-ramp-delay = <3125>;
131 nxp,dvs-run-voltage = <950000>;
132 nxp,dvs-standby-voltage = <850000>;
133 };
134
135 reg_vdd_dram: BUCK3 {
136 regulator-name = "buck3";
137 regulator-min-microvolt = <850000>;
138 regulator-max-microvolt = <950000>;
139 regulator-boot-on;
140 regulator-always-on;
141 };
142
143 reg_vdd_3v3: BUCK4 {
144 regulator-name = "buck4";
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
147 regulator-boot-on;
148 regulator-always-on;
149 };
150
151 reg_vdd_1v8: BUCK5 {
152 regulator-name = "buck5";
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <1800000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 reg_nvcc_dram: BUCK6 {
160 regulator-name = "buck6";
161 regulator-min-microvolt = <1100000>;
162 regulator-max-microvolt = <1100000>;
163 regulator-boot-on;
164 regulator-always-on;
165 };
166
167 reg_nvcc_snvs: LDO1 {
168 regulator-name = "ldo1";
169 regulator-min-microvolt = <1800000>;
170 regulator-max-microvolt = <1800000>;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174
175 reg_vdd_snvs: LDO2 {
176 regulator-name = "ldo2";
177 regulator-min-microvolt = <800000>;
Frieder Schrempffecfe772022-06-14 15:03:18 +0200[diff] [blame]178 regulator-max-microvolt = <900000>;
Frieder Schrempf9cab87f2021-09-29 16:42:42 +0200[diff] [blame]179 regulator-boot-on;
180 regulator-always-on;
181 };
182
183 reg_vdda: LDO3 {
184 regulator-name = "ldo3";
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <1800000>;
187 regulator-boot-on;
188 regulator-always-on;
189 };
190
191 reg_vdd_phy: LDO4 {
192 regulator-name = "ldo4";
193 regulator-min-microvolt = <900000>;
194 regulator-max-microvolt = <900000>;
195 regulator-boot-on;
196 regulator-always-on;
197 };
198
199 reg_nvcc_sd: LDO5 {
200 regulator-name = "ldo5";
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <3300000>;
203 };
204 };
205 };
206};
207
208&uart3 { /* console */
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_uart3>;
211 status = "okay";
212};
213
214&usdhc1 {
215 pinctrl-names = "default", "state_100mhz", "state_200mhz";
216 pinctrl-0 = <&pinctrl_usdhc1>;
217 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
218 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
219 vmmc-supply = <&reg_vdd_3v3>;
220 vqmmc-supply = <&reg_vdd_1v8>;
221 bus-width = <8>;
222 non-removable;
223 status = "okay";
224};
225
226&wdog1 {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_wdog>;
229 fsl,ext-reset-output;
230 status = "okay";
231};
232
233&iomuxc {
234 pinctrl_ecspi1: ecspi1grp {
235 fsl,pins = <
236 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
237 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
238 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
239 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
240 >;
241 };
242
243 pinctrl_i2c1: i2c1grp {
244 fsl,pins = <
245 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
246 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
247 >;
248 };
249
250 pinctrl_pmic: pmicgrp {
251 fsl,pins = <
252 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
253 MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
254 >;
255 };
256
257 pinctrl_uart3: uart3grp {
258 fsl,pins = <
259 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
260 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
261 >;
262 };
263
264 pinctrl_usdhc1: usdhc1grp {
265 fsl,pins = <
266 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
267 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
268 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
269 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
270 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
271 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
272 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
273 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
274 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
275 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
276 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
277 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
278 >;
279 };
280
281 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
282 fsl,pins = <
283 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
284 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
285 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
286 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
287 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
288 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
289 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
290 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
291 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
292 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
293 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
294 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
295 >;
296 };
297
298 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
299 fsl,pins = <
300 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
301 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
302 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
303 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
304 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
305 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
306 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
307 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
308 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
309 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
310 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
311 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
312 >;
313 };
314
315 pinctrl_wdog: wdoggrp {
316 fsl,pins = <
317 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
318 >;
319 };
320};