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Heinrich Schuchardt89d47b32022-12-31 00:08:47 +01001menu "Functionality shared between NXP SoCs"
2
Tom Rini3a581af2022-12-02 16:42:21 -05003config FSL_TRUST_ARCH_v1
4 bool
5
Tom Rini540b73a2022-06-17 16:24:31 -04006config NXP_ESBC
7 bool "NXP ESBC (secure boot) functionality"
Tom Rini3a581af2022-12-02 16:42:21 -05008 select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
9 ARCH_P5040 || ARCH_P2041
Tom Rini540b73a2022-06-17 16:24:31 -040010 help
11 Enable Freescale Secure Boot feature. Normally selected by defconfig.
12 If unsure, do not change.
13
14menu "Chain of trust / secure boot options"
Udit Agarwal5536c3c2019-11-07 16:11:32 +000015 depends on !FIT_SIGNATURE && NXP_ESBC
Tom Rini540b73a2022-06-17 16:24:31 -040016
17config CHAIN_OF_TRUST
Tom Rini28522672017-03-01 16:51:58 -050018 select FSL_CAAM
Gaurav Jain66e54712022-06-09 16:32:15 +053019 select ARCH_MISC_INIT
Tom Rini3a581af2022-12-02 16:42:21 -050020 select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
Tom Rinic9f85182022-06-16 14:04:39 -040021 select FSL_SEC_MON
Ley Foon Tan0680f1b2017-05-03 17:13:32 +080022 select SPL_BOARD_INIT if (ARM && SPL)
Alexandru Gagniuc07212092021-09-02 19:54:19 -050023 select SPL_HASH if (ARM && SPL)
Tom Rini089df182017-05-15 12:17:49 -040024 select SHA_HW_ACCEL
25 select SHA_PROG_HW_ACCEL
Simon Glass2be29652017-07-23 21:19:39 -060026 select ENV_IS_NOWHERE
Tom Rinif6c1f912022-06-25 11:02:45 -040027 select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
Sumit Garg86c773f2018-01-09 01:27:46 +053028 select CMD_EXT4 if ARM
29 select CMD_EXT4_WRITE if ARM
Tom Rini540b73a2022-06-17 16:24:31 -040030 imply CMD_BLOB
31 imply CMD_HASH if ARM
32 def_bool y
Simon Glassea7971f2017-05-17 03:25:16 -060033
34config CMD_ESBC_VALIDATE
35 bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
Tom Rini93145332022-06-16 14:04:35 -040036 default y
Simon Glassea7971f2017-05-17 03:25:16 -060037 help
38 This option enables two commands used for secure booting:
39
40 esbc_validate - validate signature using RSA verification
41 esbc_halt - put the core in spin loop (Secure Boot Only)
Rajesh Bhagat6f2d0a52018-01-17 16:13:04 +053042
Tom Rini2b2817b2022-06-16 14:04:37 -040043config ESBC_HDR_LS
44 bool
45
46config ESBC_ADDR_64BIT
47 def_bool y
48 depends on ESBC_HDR_LS && FSL_LAYERSCAPE
49 help
50 For Layerscape based platforms, ESBC image Address in Header is 64bit.
51
Tom Rini3a581af2022-12-02 16:42:21 -050052config FSL_ISBC_KEY_EXT
53 bool
54 help
55 The key used for verification of next level images is picked up from
56 an Extension Table which has been verified by the ISBC (Internal
57 Secure boot Code) in boot ROM of the SoC. The feature is only
58 applicable in case of NOR boot and is not applicable in case of
59 RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
60 for all device if IE Table is copied to XIP memory Also, for
61 Layerscape, ISBC doesn't verify this table.
62
Tom Rini601483f2022-06-16 14:04:40 -040063config SYS_FSL_SFP_BE
64 def_bool y
Tom Rini540b73a2022-06-17 16:24:31 -040065 depends on PPC || FSL_LSCH2 || ARCH_LS1021A
Tom Rini601483f2022-06-16 14:04:40 -040066
67config SYS_FSL_SFP_LE
68 def_bool y
Tom Rini540b73a2022-06-17 16:24:31 -040069 depends on !SYS_FSL_SFP_BE
Tom Rini601483f2022-06-16 14:04:40 -040070
71choice
72 prompt "SFP IP revision"
Tom Rini601483f2022-06-16 14:04:40 -040073 default SYS_FSL_SFP_VER_3_0 if PPC
74 default SYS_FSL_SFP_VER_3_4
75
76config SYS_FSL_SFP_VER_3_0
77 bool "SFP version 3.0"
78
79config SYS_FSL_SFP_VER_3_2
80 bool "SFP version 3.2"
81
82config SYS_FSL_SFP_VER_3_4
83 bool "SFP version 3.4"
84
85endchoice
86
Tom Rini5aad0a12022-06-17 16:24:32 -040087config SPL_UBOOT_KEY_HASH
88 string "Non-SRK key hash for U-Boot public/private key pair"
89 depends on SPL
90 default ""
91 help
92 Set the key hash for U-Boot here if public/private key pair used to
93 sign U-boot are different from the SRK hash put in the fuse. Example
94 of a key hash is
95 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
96 Otherwise leave this empty.
97
Tom Rinif4cd75e2022-06-17 16:24:34 -040098if PPC
99
100config BOOTSCRIPT_COPY_RAM
101 bool "Secure boot copies boot script to RAM"
102 help
103 On systems that support chain of trust booting, a number of addresses
104 are required to set variables that are used in the copying and then
105 verification of different parts of the system. If enabled, the subsequent
106 options are for what location to use in each step.
107
108config BS_ADDR_DEVICE
109 hex "Address in RAM for bs_device"
110 depends on BOOTSCRIPT_COPY_RAM
111
112config BS_SIZE
113 hex "The size of bs_size which is the amount read from bs_device"
114 depends on BOOTSCRIPT_COPY_RAM
115
116config BS_ADDR_RAM
117 hex "Address in RAM for bs_ram"
118 depends on BOOTSCRIPT_COPY_RAM
119
120config BS_HDR_ADDR_DEVICE
121 hex "Address in RAM for bs_hdr_device"
122 depends on BOOTSCRIPT_COPY_RAM
123
124config BS_HDR_SIZE
125 hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
126 depends on BOOTSCRIPT_COPY_RAM
127
128config BS_HDR_ADDR_RAM
129 hex "Address in RAM for bs_hdr_ram"
130 depends on BOOTSCRIPT_COPY_RAM
131
132config BOOTSCRIPT_HDR_ADDR
133 hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
134 default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
135
136endif
137
Tom Rini601483f2022-06-16 14:04:40 -0400138config SYS_FSL_SRK_LE
139 def_bool y
Tom Rini540b73a2022-06-17 16:24:31 -0400140 depends on ARM
Tom Rini601483f2022-06-16 14:04:40 -0400141
142config KEY_REVOCATION
143 def_bool y
Tom Rini540b73a2022-06-17 16:24:31 -0400144
145endmenu
146
Tom Rini28f9c312022-03-24 17:17:58 -0400147config DEEP_SLEEP
148 bool "Enable SoC deep sleep feature"
Tom Rini93145332022-06-16 14:04:35 -0400149 depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
150 default y
Tom Rini28f9c312022-03-24 17:17:58 -0400151 help
152 Indicates this SoC supports deep sleep feature. If deep sleep is
153 supported, core will start to execute uboot when wakes up.
154
Tom Rinia552ffc2022-06-20 08:07:44 -0400155config LAYERSCAPE_NS_ACCESS
156 bool "Layerscape non-secure access support"
157 depends on ARCH_LS1021A || FSL_LSCH2
158
Tom Rini3dc29872022-06-20 08:07:45 -0400159config PCIE1
160 bool "PCIe controller #1"
161 depends on LAYERSCAPE_NS_ACCESS || PPC
162
163config PCIE2
164 bool "PCIe controller #2"
165 depends on LAYERSCAPE_NS_ACCESS || PPC
166
167config PCIE3
168 bool "PCIe controller #3"
169 depends on LAYERSCAPE_NS_ACCESS || PPC
170
171config PCIE4
172 bool "PCIe controller #4"
173 depends on LAYERSCAPE_NS_ACCESS || PPC
174
Stephen Carlson15347d22021-06-22 16:35:20 -0700175config FSL_USE_PCA9547_MUX
176 bool "Enable PCA9547 I2C Mux on Freescale boards"
Tom Rini93145332022-06-16 14:04:35 -0400177 depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
Stephen Carlson15347d22021-06-22 16:35:20 -0700178 help
179 This option enables the PCA9547 I2C mux on Freescale boards.
180
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100181config VID
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100182 bool "Enable Freescale VID"
Tom Rini93145332022-06-16 14:04:35 -0400183 depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100184 help
185 This option enables setting core voltage based on individual
186 values saved in SoC fuses.
187
Tom Rinid06e4b72021-12-12 22:12:31 -0500188config SPL_VID
189 bool "Enable Freescale VID in SPL"
Tom Rini93145332022-06-16 14:04:35 -0400190 depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
Tom Rinid06e4b72021-12-12 22:12:31 -0500191 help
192 This option enables setting core voltage based on individual
193 values saved in SoC fuses, in SPL.
194
195if VID || SPL_VID
196
197config VID_FLS_ENV
198 string "Environment variable for overriding VDD"
199 help
200 This option allows for specifying the environment variable
201 to check to override VDD information.
202
203config VOL_MONITOR_INA220
204 bool "Enable the INA220 voltage monitor read"
205 help
206 This option enables INA220 voltage monitor read
207 functionality. It is used by the common VID driver.
208
209config VOL_MONITOR_IR36021_READ
210 bool "Enable the IR36021 voltage monitor read"
211 help
212 This option enables IR36021 voltage monitor read
213 functionality. It is used by the common VID driver.
214
215config VOL_MONITOR_IR36021_SET
216 bool "Enable the IR36021 voltage monitor set"
217 help
218 This option enables IR36021 voltage monitor set
219 functionality. It is used by the common VID driver.
220
Rajesh Bhagat6f2d0a52018-01-17 16:13:04 +0530221config VOL_MONITOR_LTC3882_READ
Rajesh Bhagat6f2d0a52018-01-17 16:13:04 +0530222 bool "Enable the LTC3882 voltage monitor read"
Rajesh Bhagat6f2d0a52018-01-17 16:13:04 +0530223 help
224 This option enables LTC3882 voltage monitor read
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100225 functionality. It is used by the common VID driver.
Rajesh Bhagat6f2d0a52018-01-17 16:13:04 +0530226
227config VOL_MONITOR_LTC3882_SET
Rajesh Bhagat6f2d0a52018-01-17 16:13:04 +0530228 bool "Enable the LTC3882 voltage monitor set"
Rajesh Bhagat6f2d0a52018-01-17 16:13:04 +0530229 help
230 This option enables LTC3882 voltage monitor set
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100231 functionality. It is used by the common VID driver.
232
233config VOL_MONITOR_ISL68233_READ
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100234 bool "Enable the ISL68233 voltage monitor read"
235 help
236 This option enables ISL68233 voltage monitor read
237 functionality. It is used by the common VID driver.
238
239config VOL_MONITOR_ISL68233_SET
Stephen Carlsonb5ee48c2021-02-08 11:11:29 +0100240 bool "Enable the ISL68233 voltage monitor set"
241 help
242 This option enables ISL68233 voltage monitor set
243 functionality. It is used by the common VID driver.
Tom Rinid06e4b72021-12-12 22:12:31 -0500244
245endif
Tom Rinid43cd482022-03-30 18:07:32 -0400246
Tom Rini1de46d92022-07-31 21:08:27 -0400247config SYS_FSL_NUM_CC_PLLS
248 int "Number of clock control PLLs"
249 depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
250 default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
251 default 6 if FSL_LSCH3 || MPC85xx
252
Tom Rini923a8552022-07-23 13:05:09 -0400253config SYS_FSL_ESDHC_BE
254 bool
255
256config SYS_FSL_IFC_BE
257 bool
258
Tom Rini89c90ca2023-01-10 11:19:41 -0500259config SYS_FSL_IFC_BANK_COUNT
260 int "Maximum banks of Integrated flash controller"
261 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
262 ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
263 ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
264 ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
265 ARCH_BSC9132
266 default 3 if ARCH_BSC9131 || ARCH_BSC9132
267 default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
268 ARCH_B4420 || ARCH_P1010
269 default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
270 ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
271 ARCH_T1024 || ARCH_T2080 || ARCH_C29X
272
Tom Rinid43cd482022-03-30 18:07:32 -0400273config FSL_QIXIS
274 bool "Enable QIXIS support"
Tom Rini93145332022-06-16 14:04:35 -0400275 depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
Tom Rinid43cd482022-03-30 18:07:32 -0400276
277config QIXIS_I2C_ACCESS
278 bool "Access to QIXIS is over i2c"
279 depends on FSL_QIXIS
280 default y
Tom Rini5cc1d922022-06-08 08:24:28 -0400281
282config HAS_FSL_DR_USB
283 def_bool y
284 depends on USB_EHCI_HCD && PPC
Tom Rini2db82bf2022-11-16 13:10:34 -0500285
286config SYS_DPAA_FMAN
287 bool
Heinrich Schuchardt89d47b32022-12-31 00:08:47 +0100288
Tom Rinia84fa1b2023-01-10 11:19:42 -0500289config SYS_FSL_SRDS_1
290 bool
291
292config SYS_FSL_SRDS_2
293 bool
294
295config SYS_HAS_SERDES
296 bool
297
Heinrich Schuchardt89d47b32022-12-31 00:08:47 +0100298endmenu