blob: 983575eb0c16a7629d27b501547c2794e37b7b05 [file] [log] [blame]
Dave Liu5f820432006-11-03 19:33:44 -06001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Dave Liu5f820432006-11-03 19:33:44 -060014 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
Dave Liu5f820432006-11-03 19:33:44 -060025/*
26 * High Level Configuration Options
27 */
28#define CONFIG_E300 1 /* E300 family */
29#define CONFIG_QE 1 /* Has QE */
30#define CONFIG_MPC83XX 1 /* MPC83XX family */
31#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
32#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
Tony Li14778582007-08-17 10:35:59 +080033#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
34#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
Dave Liu5f820432006-11-03 19:33:44 -060035
36/*
37 * System Clock Setup
38 */
39#ifdef CONFIG_PCISLAVE
40#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
41#else
42#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
43#endif
44
45#ifndef CONFIG_SYS_CLK_FREQ
46#define CONFIG_SYS_CLK_FREQ 66000000
47#endif
48
49/*
50 * Hardware Reset Configuration Word
51 */
52#define CFG_HRCW_LOW (\
53 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 HRCWL_CSB_TO_CLKIN_4X1 |\
56 HRCWL_VCO_1X2 |\
57 HRCWL_CE_PLL_VCO_DIV_4 |\
58 HRCWL_CE_PLL_DIV_1X1 |\
59 HRCWL_CE_TO_PLL_1X6 |\
60 HRCWL_CORE_TO_CSB_2X1)
61
62#ifdef CONFIG_PCISLAVE
63#define CFG_HRCW_HIGH (\
64 HRCWH_PCI_AGENT |\
65 HRCWH_PCI1_ARBITER_DISABLE |\
66 HRCWH_PCICKDRV_DISABLE |\
67 HRCWH_CORE_ENABLE |\
68 HRCWH_FROM_0XFFF00100 |\
69 HRCWH_BOOTSEQ_DISABLE |\
70 HRCWH_SW_WATCHDOG_DISABLE |\
71 HRCWH_ROM_LOC_LOCAL_16BIT)
72#else
73#define CFG_HRCW_HIGH (\
74 HRCWH_PCI_HOST |\
75 HRCWH_PCI1_ARBITER_ENABLE |\
76 HRCWH_PCICKDRV_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT)
82#endif
83
84/*
85 * System IO Config
86 */
87#define CFG_SICRH 0x00000000
88#define CFG_SICRL 0x40000000
89
90#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Tony Li14778582007-08-17 10:35:59 +080091#define CONFIG_BOARD_EARLY_INIT_R
Dave Liu5f820432006-11-03 19:33:44 -060092
93/*
94 * IMMR new address
95 */
Timur Tabid239d742006-11-03 12:00:28 -060096#define CFG_IMMR 0xE0000000
Dave Liu5f820432006-11-03 19:33:44 -060097
98/*
99 * DDR Setup
100 */
101#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
102#define CFG_SDRAM_BASE CFG_DDR_BASE
103#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
Xie Xiaobob110f402007-02-14 18:27:06 +0800104#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
105 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Dave Liu5f820432006-11-03 19:33:44 -0600106
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600107#define CFG_83XX_DDR_USES_CS0
108
Xie Xiaobob110f402007-02-14 18:27:06 +0800109#define CONFIG_DDR_ECC /* support DDR ECC function */
Dave Liu5f820432006-11-03 19:33:44 -0600110#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
111
Xie Xiaobob110f402007-02-14 18:27:06 +0800112/*
113 * DDRCDR - DDR Control Driver Register
114 */
115#define CFG_DDRCDR_VALUE 0x80080001
116
Dave Liu5f820432006-11-03 19:33:44 -0600117#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
118#if defined(CONFIG_SPD_EEPROM)
119/*
120 * Determine DDR configuration from I2C interface.
121 */
122#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
123#else
124/*
125 * Manually set up DDR parameters
126 */
127#define CFG_DDR_SIZE 256 /* MB */
Xie Xiaobob110f402007-02-14 18:27:06 +0800128#if defined(CONFIG_DDR_II)
129#define CFG_DDRCDR 0x80080001
130#define CFG_DDR_CS0_BNDS 0x0000000f
131#define CFG_DDR_CS0_CONFIG 0x80330102
132#define CFG_DDR_TIMING_0 0x00220802
133#define CFG_DDR_TIMING_1 0x38357322
134#define CFG_DDR_TIMING_2 0x2f9048c8
135#define CFG_DDR_TIMING_3 0x00000000
136#define CFG_DDR_CLK_CNTL 0x02000000
137#define CFG_DDR_MODE 0x47d00432
138#define CFG_DDR_MODE2 0x8000c000
139#define CFG_DDR_INTERVAL 0x03cf0080
140#define CFG_DDR_SDRAM_CFG 0x43000000
141#define CFG_DDR_SDRAM_CFG2 0x00401000
142#else
Dave Liu5f820432006-11-03 19:33:44 -0600143#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
144#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
145#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100146#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
Dave Liu5f820432006-11-03 19:33:44 -0600147#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
148#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
149#endif
Xie Xiaobob110f402007-02-14 18:27:06 +0800150#endif
Dave Liu5f820432006-11-03 19:33:44 -0600151
152/*
153 * Memory test
154 */
155#undef CFG_DRAM_TEST /* memory test, takes time */
156#define CFG_MEMTEST_START 0x00000000 /* memtest region */
157#define CFG_MEMTEST_END 0x00100000
158
159/*
160 * The reserved memory
161 */
162
163#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
164
165#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
166#define CFG_RAMBOOT
167#else
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100168#undef CFG_RAMBOOT
Dave Liu5f820432006-11-03 19:33:44 -0600169#endif
170
Timur Tabib2893e12007-11-05 09:34:06 -0600171/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
Dave Liu5f820432006-11-03 19:33:44 -0600172#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
173#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
174
175/*
176 * Initial RAM Base Address Setup
177 */
178#define CFG_INIT_RAM_LOCK 1
179#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
180#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
181#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
182#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
183
184/*
185 * Local Bus Configuration & Clock Setup
186 */
187#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
188#define CFG_LBC_LBCR 0x00000000
189
190/*
191 * FLASH on the Local Bus
192 */
193#define CFG_FLASH_CFI /* use the Common Flash Interface */
194#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
195#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
Xie Xiaobob110f402007-02-14 18:27:06 +0800196#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
Jerry Van Baren82e45a22008-03-18 21:44:41 -0400197#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Dave Liu5f820432006-11-03 19:33:44 -0600198
199#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
200#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
201
202#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
203 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
204 BR_V) /* valid */
Xie Xiaobob110f402007-02-14 18:27:06 +0800205#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
206 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
207 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
Dave Liu5f820432006-11-03 19:33:44 -0600208
209#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
Xie Xiaobob110f402007-02-14 18:27:06 +0800210#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu5f820432006-11-03 19:33:44 -0600211
212#undef CFG_FLASH_CHECKSUM
213
214/*
215 * BCSR on the Local Bus
216 */
217#define CFG_BCSR 0xF8000000
218#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
Dave Liua87c8562007-01-19 10:43:26 +0800219#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
Dave Liu5f820432006-11-03 19:33:44 -0600220
221#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
222#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
223
224/*
225 * SDRAM on the Local Bus
226 */
227#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
228#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
229
230#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
231
232#ifdef CFG_LB_SDRAM
233#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
234#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
235
236/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
237/*
238 * Base Register 2 and Option Register 2 configure SDRAM.
239 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
240 *
241 * For BR2, need:
242 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
243 * port size = 32-bits = BR2[19:20] = 11
244 * no parity checking = BR2[21:22] = 00
245 * SDRAM for MSEL = BR2[24:26] = 011
246 * Valid = BR[31] = 1
247 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100248 * 0 4 8 12 16 20 24 28
Dave Liu5f820432006-11-03 19:33:44 -0600249 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
250 *
251 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
252 * the top 17 bits of BR2.
253 */
254
255#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
256
257/*
258 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
259 *
260 * For OR2, need:
261 * 64MB mask for AM, OR2[0:7] = 1111 1100
262 * XAM, OR2[17:18] = 11
263 * 9 columns OR2[19-21] = 010
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100264 * 13 rows OR2[23-25] = 100
Dave Liu5f820432006-11-03 19:33:44 -0600265 * EAD set for extra time OR[31] = 1
266 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100267 * 0 4 8 12 16 20 24 28
Dave Liu5f820432006-11-03 19:33:44 -0600268 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
269 */
270
271#define CFG_OR2_PRELIM 0xfc006901
272
273#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
274#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
275
276/*
277 * LSDMR masks
278 */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100279#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
280#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
281#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
Dave Liu5f820432006-11-03 19:33:44 -0600282#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
283#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100284#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
285#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
Dave Liu5f820432006-11-03 19:33:44 -0600286#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
287
288#define CFG_LBC_LSDMR_COMMON 0x0063b723
289
290/*
291 * SDRAM Controller configuration sequence.
292 */
293#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
294 | CFG_LBC_LSDMR_OP_PCHALL)
295#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
296 | CFG_LBC_LSDMR_OP_ARFRSH)
297#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
298 | CFG_LBC_LSDMR_OP_ARFRSH)
299#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
300 | CFG_LBC_LSDMR_OP_MRW)
301#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
302 | CFG_LBC_LSDMR_OP_NORMAL)
303
304#endif
305
306/*
307 * Windows to access PIB via local bus
308 */
Dave Liua87c8562007-01-19 10:43:26 +0800309#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
310#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
Dave Liu5f820432006-11-03 19:33:44 -0600311
312/*
313 * CS4 on Local Bus, to PIB
314 */
Tony Li14778582007-08-17 10:35:59 +0800315#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
Dave Liu5f820432006-11-03 19:33:44 -0600316#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
317
318/*
319 * CS5 on Local Bus, to PIB
320 */
Tony Li14778582007-08-17 10:35:59 +0800321#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
Dave Liu5f820432006-11-03 19:33:44 -0600322#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
323
324/*
325 * Serial Port
326 */
327#define CONFIG_CONS_INDEX 1
328#undef CONFIG_SERIAL_SOFTWARE_FIFO
329#define CFG_NS16550
330#define CFG_NS16550_SERIAL
331#define CFG_NS16550_REG_SIZE 1
332#define CFG_NS16550_CLK get_bus_freq(0)
333
334#define CFG_BAUDRATE_TABLE \
335 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
336
Timur Tabid239d742006-11-03 12:00:28 -0600337#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
338#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
Dave Liu5f820432006-11-03 19:33:44 -0600339
Kim Phillips22d71a72007-02-27 18:41:08 -0600340#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Dave Liu5f820432006-11-03 19:33:44 -0600341/* Use the HUSH parser */
342#define CFG_HUSH_PARSER
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100343#ifdef CFG_HUSH_PARSER
Dave Liu5f820432006-11-03 19:33:44 -0600344#define CFG_PROMPT_HUSH_PS2 "> "
345#endif
346
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600347/* pass open firmware flat tree */
Gerald Van Baren213bf8c2007-03-31 12:23:51 -0400348#define CONFIG_OF_LIBFDT 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600349#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600350#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600351
Dave Liu5f820432006-11-03 19:33:44 -0600352/* I2C */
353#define CONFIG_HARD_I2C /* I2C with hardware support */
354#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Timur Tabibe5e6182006-11-03 19:15:00 -0600355#define CONFIG_FSL_I2C
356#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
Dave Liu5f820432006-11-03 19:33:44 -0600357#define CFG_I2C_SLAVE 0x7F
358#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */
359#define CFG_I2C_OFFSET 0x3000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100360#define CFG_I2C2_OFFSET 0x3100
Dave Liu5f820432006-11-03 19:33:44 -0600361
362/*
363 * Config on-board RTC
364 */
365#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
366#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
367
368/*
369 * General PCI
370 * Addresses are mapped 1-1.
371 */
372#define CFG_PCI_MEM_BASE 0x80000000
373#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
374#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
375#define CFG_PCI_MMIO_BASE 0x90000000
376#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
377#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
Scott Wooda7ba32d2008-03-24 12:44:13 -0500378#define CFG_PCI_IO_BASE 0x00000000
Dave Liu5f820432006-11-03 19:33:44 -0600379#define CFG_PCI_IO_PHYS 0xE0300000
380#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
381
382#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
383#define CFG_PCI_SLV_MEM_BUS 0x00000000
384#define CFG_PCI_SLV_MEM_SIZE 0x80000000
385
386
387#ifdef CONFIG_PCI
388
389#define CONFIG_NET_MULTI
390#define CONFIG_PCI_PNP /* do pci plug-and-play */
391
392#undef CONFIG_EEPRO100
393#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100394#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu5f820432006-11-03 19:33:44 -0600395
396#endif /* CONFIG_PCI */
397
398
399#ifndef CONFIG_NET_MULTI
400#define CONFIG_NET_MULTI 1
401#endif
402
403/*
Dave Liu7737d5c2006-11-03 12:11:15 -0600404 * QE UEC ethernet configuration
405 */
406#define CONFIG_UEC_ETH
Kim Phillips711a7942008-01-15 14:05:14 -0600407#define CONFIG_ETHPRIME "FSL UEC0"
Dave Liu7737d5c2006-11-03 12:11:15 -0600408#define CONFIG_PHY_MODE_NEED_CHANGE
409
410#define CONFIG_UEC_ETH1 /* GETH1 */
411
412#ifdef CONFIG_UEC_ETH1
413#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
414#define CFG_UEC1_RX_CLK QE_CLK_NONE
415#define CFG_UEC1_TX_CLK QE_CLK9
416#define CFG_UEC1_ETH_TYPE GIGA_ETH
417#define CFG_UEC1_PHY_ADDR 0
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100418#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
Dave Liu7737d5c2006-11-03 12:11:15 -0600419#endif
420
421#define CONFIG_UEC_ETH2 /* GETH2 */
422
423#ifdef CONFIG_UEC_ETH2
424#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
425#define CFG_UEC2_RX_CLK QE_CLK_NONE
426#define CFG_UEC2_TX_CLK QE_CLK4
427#define CFG_UEC2_ETH_TYPE GIGA_ETH
428#define CFG_UEC2_PHY_ADDR 1
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100429#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
Dave Liu7737d5c2006-11-03 12:11:15 -0600430#endif
431
432/*
Dave Liu5f820432006-11-03 19:33:44 -0600433 * Environment
434 */
435
436#ifndef CFG_RAMBOOT
437 #define CFG_ENV_IS_IN_FLASH 1
Timur Tabib2893e12007-11-05 09:34:06 -0600438 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
439 #define CFG_ENV_SECT_SIZE 0x20000
Dave Liu5f820432006-11-03 19:33:44 -0600440 #define CFG_ENV_SIZE 0x2000
441#else
442 #define CFG_NO_FLASH 1 /* Flash is not usable now */
443 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
444 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
445 #define CFG_ENV_SIZE 0x2000
446#endif
447
448#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
449#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
450
Jon Loeliger8ea54992007-07-04 22:30:06 -0500451/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500452 * BOOTP options
453 */
454#define CONFIG_BOOTP_BOOTFILESIZE
455#define CONFIG_BOOTP_BOOTPATH
456#define CONFIG_BOOTP_GATEWAY
457#define CONFIG_BOOTP_HOSTNAME
458
459
460/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500461 * Command line configuration.
462 */
463#include <config_cmd_default.h>
464
465#define CONFIG_CMD_PING
466#define CONFIG_CMD_I2C
467#define CONFIG_CMD_ASKENV
Jerry Van Barenb5cdd7d2008-01-12 13:24:14 -0500468#define CONFIG_CMD_SDRAM
Jon Loeliger8ea54992007-07-04 22:30:06 -0500469
Dave Liu5f820432006-11-03 19:33:44 -0600470#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500471 #define CONFIG_CMD_PCI
Dave Liu5f820432006-11-03 19:33:44 -0600472#endif
473
Jon Loeliger8ea54992007-07-04 22:30:06 -0500474#if defined(CFG_RAMBOOT)
475 #undef CONFIG_CMD_ENV
476 #undef CONFIG_CMD_LOADS
477#endif
478
Dave Liu5f820432006-11-03 19:33:44 -0600479
480#undef CONFIG_WATCHDOG /* watchdog disabled */
481
482/*
483 * Miscellaneous configurable options
484 */
485#define CFG_LONGHELP /* undef to save memory */
486#define CFG_LOAD_ADDR 0x2000000 /* default load address */
487#define CFG_PROMPT "=> " /* Monitor Command Prompt */
488
Jon Loeliger8ea54992007-07-04 22:30:06 -0500489#if defined(CONFIG_CMD_KGDB)
Dave Liu5f820432006-11-03 19:33:44 -0600490 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
491#else
492 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
493#endif
494
495#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
496#define CFG_MAXARGS 16 /* max number of command args */
497#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
498#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
499
500/*
501 * For booting Linux, the board info and command line data
502 * have to be in the first 8 MB of memory, since this is
503 * the maximum mapped by the Linux kernel during initialization.
504 */
505#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
506
507/*
508 * Core HID Setup
509 */
510#define CFG_HID0_INIT 0x000000000
511#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
512#define CFG_HID2 HID2_HBE
513
514/*
Dave Liu5f820432006-11-03 19:33:44 -0600515 * MMU Setup
516 */
517
518/* DDR: cache cacheable */
519#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
520#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
521#define CFG_DBAT0L CFG_IBAT0L
522#define CFG_DBAT0U CFG_IBAT0U
523
524/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Timur Tabid239d742006-11-03 12:00:28 -0600525#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600526 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Timur Tabid239d742006-11-03 12:00:28 -0600527#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
Dave Liu5f820432006-11-03 19:33:44 -0600528#define CFG_DBAT1L CFG_IBAT1L
529#define CFG_DBAT1U CFG_IBAT1U
530
531/* BCSR: cache-inhibit and guarded */
532#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
533 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
534#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
535#define CFG_DBAT2L CFG_IBAT2L
536#define CFG_DBAT2U CFG_IBAT2U
537
538/* FLASH: icache cacheable, but dcache-inhibit and guarded */
539#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
540#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
541#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
542 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
543#define CFG_DBAT3U CFG_IBAT3U
544
545/* Local bus SDRAM: cacheable */
546#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
547#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
548#define CFG_DBAT4L CFG_IBAT4L
549#define CFG_DBAT4U CFG_IBAT4U
550
551/* Stack in dcache: cacheable, no memory coherence */
552#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
553#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
554#define CFG_DBAT5L CFG_IBAT5L
555#define CFG_DBAT5U CFG_IBAT5U
556
557#ifdef CONFIG_PCI
558/* PCI MEM space: cacheable */
559#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
560#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
561#define CFG_DBAT6L CFG_IBAT6L
562#define CFG_DBAT6U CFG_IBAT6U
563/* PCI MMIO space: cache-inhibit and guarded */
564#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
565 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
566#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
567#define CFG_DBAT7L CFG_IBAT7L
568#define CFG_DBAT7U CFG_IBAT7U
569#else
570#define CFG_IBAT6L (0)
571#define CFG_IBAT6U (0)
572#define CFG_IBAT7L (0)
573#define CFG_IBAT7U (0)
574#define CFG_DBAT6L CFG_IBAT6L
575#define CFG_DBAT6U CFG_IBAT6U
576#define CFG_DBAT7L CFG_IBAT7L
577#define CFG_DBAT7U CFG_IBAT7U
578#endif
579
580/*
581 * Internal Definitions
582 *
583 * Boot Flags
584 */
585#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
586#define BOOTFLAG_WARM 0x02 /* Software reboot */
587
Jon Loeliger8ea54992007-07-04 22:30:06 -0500588#if defined(CONFIG_CMD_KGDB)
Dave Liu5f820432006-11-03 19:33:44 -0600589#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
590#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
591#endif
592
593/*
594 * Environment Configuration
595 */
596
597#define CONFIG_ENV_OVERWRITE
598
599#if defined(CONFIG_UEC_ETH)
Kim Phillips977b5752008-01-09 15:24:06 -0600600#define CONFIG_HAS_ETH0
Dave Liu5f820432006-11-03 19:33:44 -0600601#define CONFIG_ETHADDR 00:04:9f:ef:01:01
602#define CONFIG_HAS_ETH1
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100603#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
Dave Liu5f820432006-11-03 19:33:44 -0600604#endif
605
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100606#define CONFIG_BAUDRATE 115200
Dave Liu5f820432006-11-03 19:33:44 -0600607
Kim Phillipsb2115752008-04-24 14:07:38 -0500608#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
Dave Liu5f820432006-11-03 19:33:44 -0600609
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100610#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
611#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Dave Liu5f820432006-11-03 19:33:44 -0600612
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100613#define CONFIG_EXTRA_ENV_SETTINGS \
614 "netdev=eth0\0" \
615 "consoledev=ttyS0\0" \
616 "ramdiskaddr=1000000\0" \
Dave Liu5f820432006-11-03 19:33:44 -0600617 "ramdiskfile=ramfs.83xx\0" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600618 "fdtaddr=400000\0" \
Kim Phillips270fe262008-03-07 12:27:31 -0600619 "fdtfile=mpc836x_mds.dtb\0" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600620 ""
Dave Liu5f820432006-11-03 19:33:44 -0600621
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100622#define CONFIG_NFSBOOTCOMMAND \
623 "setenv bootargs root=/dev/nfs rw " \
624 "nfsroot=$serverip:$rootpath " \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600625 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100626 "console=$consoledev,$baudrate $othbootargs;" \
627 "tftp $loadaddr $bootfile;" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600628 "tftp $fdtaddr $fdtfile;" \
629 "bootm $loadaddr - $fdtaddr"
Dave Liu5f820432006-11-03 19:33:44 -0600630
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600631#define CONFIG_RAMBOOTCOMMAND \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100632 "setenv bootargs root=/dev/ram rw " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "tftp $ramdiskaddr $ramdiskfile;" \
635 "tftp $loadaddr $bootfile;" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr $ramdiskaddr $fdtaddr"
638
Dave Liu5f820432006-11-03 19:33:44 -0600639
640#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
641
642#endif /* __CONFIG_H */