blob: 2ce39c913c831a2e873ca04ddef34a4b07b727ed [file] [log] [blame]
Stefan Roese5e4b3362005-08-22 17:51:53 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*************************************************************************
25 * (c) 2005 esd gmbh Hannover
26 *
27 *
28 * from IceCube.h file
29 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
30 *
31 *************************************************************************/
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
42#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
43#define CONFIG_ICECUBE 1 /* ... on IceCube board */
44#define CONFIG_PF5200 1 /* ... on PF5200 board */
45#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
46
47#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
48
49#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
50#define BOOTFLAG_WARM 0x02 /* Software reboot */
51
Stefan Roese5e4b3362005-08-22 17:51:53 +020052/*
53 * Serial console configuration
54 */
55#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
56#if 0 /* test-only */
57#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
58#else
59#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
60#endif
61#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
62
63#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
64/*
65 * PCI Mapping:
66 * 0x40000000 - 0x4fffffff - PCI Memory
67 * 0x50000000 - 0x50ffffff - PCI IO Space
68 */
69#define CONFIG_PCI 1
70#define CONFIG_PCI_PNP 1
71#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050072#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Stefan Roese5e4b3362005-08-22 17:51:53 +020073
74#define CONFIG_PCI_MEM_BUS 0x40000000
75#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
76#define CONFIG_PCI_MEM_SIZE 0x10000000
77
78#define CONFIG_PCI_IO_BUS 0x50000000
79#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
80#define CONFIG_PCI_IO_SIZE 0x01000000
81
Marian Balakowicz63ff0042005-10-28 22:30:33 +020082#define CONFIG_MII 1
Stefan Roese5e4b3362005-08-22 17:51:53 +020083#if 0 /* test-only !!! */
84#define CONFIG_NET_MULTI 1
85#define CONFIG_EEPRO100 1
86#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
87#define CONFIG_NS8382X 1
88#endif
Stefan Roese5e4b3362005-08-22 17:51:53 +020089#endif
90
91/* Partitions */
92#define CONFIG_MAC_PARTITION
93#define CONFIG_DOS_PARTITION
94
95/* USB */
96#if 0
97#define CONFIG_USB_OHCI
Stefan Roese5e4b3362005-08-22 17:51:53 +020098#define CONFIG_USB_STORAGE
Stefan Roese5e4b3362005-08-22 17:51:53 +020099#endif
100
Stefan Roese5e4b3362005-08-22 17:51:53 +0200101
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500102/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500103 * BOOTP options
104 */
105#define CONFIG_BOOTP_BOOTFILESIZE
106#define CONFIG_BOOTP_BOOTPATH
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109
110
111/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500112 * Command line configuration.
113 */
114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_BSP
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500117#define CONFIG_CMD_EEPROM
118#define CONFIG_CMD_ELF
119#define CONFIG_CMD_FAT
120#define CONFIG_CMD_I2C
121#define CONFIG_CMD_IDE
122
Jon Loeliger079a1362007-07-10 10:12:10 -0500123#ifdef CONFIG_MPC5200
124#define CONFIG_CMD_PCI
125#endif
126
Stefan Roese5e4b3362005-08-22 17:51:53 +0200127
128#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
129# define CFG_LOWBOOT 1
130# define CFG_LOWBOOT16 1
131#endif
132#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
133# define CFG_LOWBOOT 1
134# define CFG_LOWBOOT08 1
135#endif
136
137/*
138 * Autobooting
139 */
140#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
141
142#define CONFIG_PREBOOT "echo;" \
143 "echo Welcome to ParaFinder pf5200;" \
144 "echo"
145
146#undef CONFIG_BOOTARGS
147
148#define CONFIG_EXTRA_ENV_SETTINGS \
149 "netdev=eth0\0" \
150 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
151 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100152 "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
153 "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
154 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
Stefan Roese5e4b3362005-08-22 17:51:53 +0200155 "loadaddr=01000000\0" \
156 "serverip=192.168.2.99\0" \
157 "gatewayip=10.0.0.79\0" \
158 "user=mu\0" \
159 "target=pf5200.esd\0" \
160 "script=pf5200.bat\0" \
161 "image=/tftpboot/vxWorks_pf5200\0" \
162 "ipaddr=10.0.13.196\0" \
163 "netmask=255.255.0.0\0" \
164 ""
165
166#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
167
168#if defined(CONFIG_MPC5200)
169/*
170 * IPB Bus clocking configuration.
171 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200172#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200173#endif
174/*
175 * I2C configuration
176 */
177#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
178#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
179
180#define CFG_I2C_SPEED 86000 /* 100 kHz */
181#define CFG_I2C_SLAVE 0x7F
182
183/*
184 * EEPROM configuration
185 */
186#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
187#define CFG_I2C_EEPROM_ADDR_LEN 2
188#define CFG_EEPROM_PAGE_WRITE_BITS 5
189#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
190#define CFG_I2C_MULTI_EEPROMS 1
191/*
192 * Flash configuration
193 */
194#define CFG_FLASH_BASE 0xFE000000
195#define CFG_FLASH_SIZE 0x02000000
196#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
197#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
198#define CFG_MAX_FLASH_SECT 512
199
200#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
201#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
202
203/*
204 * Environment settings
205 */
206#if 1 /* test-only */
207#define CFG_ENV_IS_IN_FLASH 0
208#define CFG_ENV_SIZE 0x10000
209#define CFG_ENV_SECT_SIZE 0x10000
210#define CONFIG_ENV_OVERWRITE 1
211#else
212#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
213#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
214#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
215 /* total size of a CAT24WC32 is 8192 bytes */
216#define CONFIG_ENV_OVERWRITE 1
217#endif
218
219/*
220 * Memory map
221 */
222#define CFG_MBAR 0xF0000000
223#define CFG_SDRAM_BASE 0x00000000
224#define CFG_DEFAULT_MBAR 0x80000000
225
226/* Use SRAM until RAM will be available */
227#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
228#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
229
230#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
231#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
232#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
233
234#define CFG_MONITOR_BASE TEXT_BASE
235#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
236# define CFG_RAMBOOT 1
237#endif
238
239#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
240#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
241#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
242
243/*
244 * Ethernet configuration
245 */
246#define CONFIG_MPC5xxx_FEC 1
247/*
248 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
249 */
250/* #define CONFIG_FEC_10MBIT 1 */
251#define CONFIG_PHY_ADDR 0x00
252#define CONFIG_UDP_CHECKSUM 1
253
254/*
255 * GPIO configuration
256 */
257#define CFG_GPS_PORT_CONFIG 0x01052444
258
259/*
260 * Miscellaneous configurable options
261 */
262#define CFG_LONGHELP /* undef to save memory */
263#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500264#if defined(CONFIG_CMD_KGDB)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200265#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
266#else
267#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
268#endif
269#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
270#define CFG_MAXARGS 16 /* max number of command args */
271#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
272
273#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
274#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
275
276#define CFG_LOAD_ADDR 0x100000 /* default load address */
277
278#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
279
280#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
281
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500282#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
283#if defined(CONFIG_CMD_KGDB)
284# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
285#endif
286
Stefan Roese5e4b3362005-08-22 17:51:53 +0200287/*
288 * Various low-level settings
289 */
290#if defined(CONFIG_MPC5200)
291#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
292#define CFG_HID0_FINAL HID0_ICE
293#else
294#define CFG_HID0_INIT 0
295#define CFG_HID0_FINAL 0
296#endif
297
298#define CFG_BOOTCS_START CFG_FLASH_BASE
299#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
300#define CFG_BOOTCS_CFG 0x0004DD00
301
302#define CFG_CS0_START CFG_FLASH_BASE
303#define CFG_CS0_SIZE CFG_FLASH_SIZE
304
305#define CFG_CS1_START 0xfd000000
306#define CFG_CS1_SIZE 0x00010000
307#define CFG_CS1_CFG 0x10101410
308
309#define CFG_CS_BURST 0x00000000
310#define CFG_CS_DEADCYCLE 0x33333333
311
312#define CFG_RESET_ADDRESS 0xff000000
313
314/*-----------------------------------------------------------------------
315 * USB stuff
316 *-----------------------------------------------------------------------
317 */
318#define CONFIG_USB_CLOCK 0x0001BBBB
319#define CONFIG_USB_CONFIG 0x00001000
320
321/*-----------------------------------------------------------------------
322 * IDE/ATA stuff Supports IDE harddisk
323 *-----------------------------------------------------------------------
324 */
325
326#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
327
328#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
329#undef CONFIG_IDE_LED /* LED for ide not supported */
330
331#define CONFIG_IDE_RESET /* reset for ide supported */
332#define CONFIG_IDE_PREINIT
333
334#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
335#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
336
337#define CFG_ATA_IDE0_OFFSET 0x0000
338
339#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
340
341/* Offset for data I/O */
342#define CFG_ATA_DATA_OFFSET (0x0060)
343
344/* Offset for normal register accesses */
345#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
346
347/* Offset for alternate registers */
348#define CFG_ATA_ALT_OFFSET (0x005C)
349
350/* Interval between registers */
351#define CFG_ATA_STRIDE 4
352
353/*-----------------------------------------------------------------------
354 * CPLD stuff
355 */
356#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
357#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
358
359/* CPLD program pin configuration */
360#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
361#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
362#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
363#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
364
365#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
366#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
367#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
368#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
369
370#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
371#define JTAG_GPIO_CFG_SET 0x00000000
372#define JTAG_GPIO_CFG_RESET 0x00F00000
373
374#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
375#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
376#define JTAG_GPIO_TMS_EN_RESET 0x00000000
377#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
378#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
379#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
380
381#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
382#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
383#define JTAG_GPIO_TCK_EN_RESET 0x00000000
384#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
385#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
386#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
387
388#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
389#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
390#define JTAG_GPIO_TDI_EN_RESET 0x00000000
391#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
392#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
393#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
394
395#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
396#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
397#define JTAG_GPIO_TDO_EN_RESET 0x00000000
398#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
399#define JTAG_GPIO_TDO_DDR_SET 0x00000000
400#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
401
402#endif /* __CONFIG_H */