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Bo Shenf7fa2f32012-07-05 17:21:46 +00001/*
2 * Copyright (C) 2012 Atmel Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/io.h>
25#include <asm/arch/at91sam9x5_matrix.h>
26#include <asm/arch/at91sam9_smc.h>
27#include <asm/arch/at91_common.h>
28#include <asm/arch/at91_pmc.h>
29#include <asm/arch/at91_rstc.h>
30#include <asm/arch/gpio.h>
31#include <asm/arch/clk.h>
32#include <lcd.h>
33#include <atmel_hlcdc.h>
34#ifdef CONFIG_MACB
35#include <net.h>
36#endif
37#include <netdev.h>
38#ifdef CONFIG_LCD_INFO
39#include <nand.h>
40#include <version.h>
41#endif
42#ifdef CONFIG_ATMEL_SPI
43#include <spi.h>
44#endif
45
46DECLARE_GLOBAL_DATA_PTR;
47
48/* ------------------------------------------------------------------------- */
49/*
50 * Miscelaneous platform dependent initialisations
51 */
52#ifdef CONFIG_CMD_NAND
53static void at91sam9x5ek_nand_hw_init(void)
54{
55 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
56 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
57 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
58 unsigned long csa;
59
60 /* Enable CS3 */
61 csa = readl(&matrix->ebicsa);
62 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
Bo Shen4ed9c882012-08-15 18:44:27 +000063 /* NAND flash on D16 */
64 csa |= AT91_MATRIX_NFD0_ON_D16;
Bo Shenf7fa2f32012-07-05 17:21:46 +000065 writel(csa, &matrix->ebicsa);
66
67 /* Configure SMC CS3 for NAND/SmartMedia */
Wu, Josh2ab4c742012-08-23 00:05:37 +000068 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
69 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
Bo Shenf7fa2f32012-07-05 17:21:46 +000070 &smc->cs[3].setup);
Wu, Josh2ab4c742012-08-23 00:05:37 +000071 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
72 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
Bo Shenf7fa2f32012-07-05 17:21:46 +000073 &smc->cs[3].pulse);
Wu, Josh2ab4c742012-08-23 00:05:37 +000074 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
Bo Shenf7fa2f32012-07-05 17:21:46 +000075 &smc->cs[3].cycle);
76 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
77 AT91_SMC_MODE_EXNW_DISABLE |
78#ifdef CONFIG_SYS_NAND_DBW_16
79 AT91_SMC_MODE_DBW_16 |
80#else /* CONFIG_SYS_NAND_DBW_8 */
81 AT91_SMC_MODE_DBW_8 |
82#endif
Wu, Josh2ab4c742012-08-23 00:05:37 +000083 AT91_SMC_MODE_TDF_CYCLE(1),
Bo Shenf7fa2f32012-07-05 17:21:46 +000084 &smc->cs[3].mode);
85
86 writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
87
88 /* Configure RDY/BSY */
89 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
90 /* Enable NandFlash */
91 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
92
93 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
94 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
95 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
96 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
97 at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
98 at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
99 at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
100 at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
101 at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
102 at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
103 at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
104 at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
105}
106#endif
107
108int board_eth_init(bd_t *bis)
109{
110 int rc = 0;
111
112#ifdef CONFIG_MACB
113 if (has_emac0())
114 rc = macb_eth_initialize(0,
115 (void *)ATMEL_BASE_EMAC0, 0x00);
116 if (has_emac1())
117 rc = macb_eth_initialize(1,
118 (void *)ATMEL_BASE_EMAC1, 0x00);
119#endif
120 return rc;
121}
122
123#ifdef CONFIG_LCD
124vidinfo_t panel_info = {
125 .vl_col = 800,
126 .vl_row = 480,
127 .vl_clk = 24000000,
128 .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
129 .vl_bpix = LCD_BPP,
130 .vl_tft = 1,
131 .vl_clk_pol = 1,
132 .vl_hsync_len = 128,
133 .vl_left_margin = 64,
134 .vl_right_margin = 64,
135 .vl_vsync_len = 2,
136 .vl_upper_margin = 22,
137 .vl_lower_margin = 21,
138 .mmio = ATMEL_BASE_LCDC,
139};
140
141void lcd_enable(void)
142{
143 if (has_lcdc())
144 at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
145}
146
147void lcd_disable(void)
148{
149 if (has_lcdc())
150 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
151}
152
153static void at91sam9x5ek_lcd_hw_init(void)
154{
155 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
156
157 if (has_lcdc()) {
158 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
159 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
160 at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
161 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
162 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
163 at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
164
165 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
166 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
167 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
168 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
169 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
170 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
171 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
172 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
173 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
174 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
175 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
176 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
177 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
178 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
179 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
180 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
181 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
182 at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
183 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
184 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
185 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
186 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
187 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
188 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
189
190 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
191 }
192}
193
194#ifdef CONFIG_LCD_INFO
195void lcd_show_board_info(void)
196{
197 ulong dram_size, nand_size;
198 int i;
199 char temp[32];
200
201 if (has_lcdc()) {
202 lcd_printf("%s\n", U_BOOT_VERSION);
203 lcd_printf("(C) 2012 ATMEL Corp\n");
204 lcd_printf("at91support@atmel.com\n");
205 lcd_printf("%s CPU at %s MHz\n",
206 get_cpu_name(),
207 strmhz(temp, get_cpu_clk_rate()));
208
209 dram_size = 0;
210 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
211 dram_size += gd->bd->bi_dram[i].size;
212 nand_size = 0;
213 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
214 nand_size += nand_info[i].size;
215 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
216 dram_size >> 20,
217 nand_size >> 20);
218 }
219}
220#endif /* CONFIG_LCD_INFO */
221#endif /* CONFIG_LCD */
222
223/* SPI chip select control */
224#ifdef CONFIG_ATMEL_SPI
225int spi_cs_is_valid(unsigned int bus, unsigned int cs)
226{
227 return bus == 0 && cs < 2;
228}
229
230void spi_cs_activate(struct spi_slave *slave)
231{
232 switch (slave->cs) {
233 case 1:
234 at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
235 break;
236 case 0:
237 default:
238 at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
239 break;
240 }
241}
242
243void spi_cs_deactivate(struct spi_slave *slave)
244{
245 switch (slave->cs) {
246 case 1:
247 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
248 break;
249 case 0:
250 default:
251 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
252 break;
253 }
254}
255#endif /* CONFIG_ATMEL_SPI */
256
257int board_early_init_f(void)
258{
259 at91_seriald_hw_init();
260 return 0;
261}
262
263int board_init(void)
264{
265 /* arch number of AT91SAM9X5EK-Board */
266 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
267
268 /* adress of boot parameters */
269 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
270
271#ifdef CONFIG_CMD_NAND
272 at91sam9x5ek_nand_hw_init();
273#endif
274
275#ifdef CONFIG_ATMEL_SPI
276 at91_spi0_hw_init(1 << 0);
277 at91_spi0_hw_init(1 << 4);
278#endif
279
280#ifdef CONFIG_MACB
281 at91_macb_hw_init();
282#endif
283
284#ifdef CONFIG_LCD
285 at91sam9x5ek_lcd_hw_init();
286#endif
287 return 0;
288}
289
290int dram_init(void)
291{
292 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
293 CONFIG_SYS_SDRAM_SIZE);
294 return 0;
295}