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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 2af181b53e286e90c3b36ba608c1c7b209e8ad8e / . / arch / arm / dts / imx6qdl-gw5910.dtsi
blob: 248e077a56edf362d5da5ee15c0cde5360ab5d51 [file] [log] [blame]
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
Tim Harvey19a387f2021-03-01 14:33:35 -0800[diff] [blame]16 mmc0 = &usdhc3;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]17 };
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
23 memory@10000000 {
24 device_type = "memory";
25 reg = <0x10000000 0x20000000>;
26 };
27
28 gpio-keys {
29 compatible = "gpio-keys";
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 user-pb {
34 label = "user_pb";
35 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
36 linux,code = <BTN_0>;
37 };
38
39 user-pb1x {
40 label = "user_pb1x";
41 linux,code = <BTN_1>;
42 interrupt-parent = <&gsc>;
43 interrupts = <0>;
44 };
45
46 key-erased {
47 label = "key-erased";
48 linux,code = <BTN_2>;
49 interrupt-parent = <&gsc>;
50 interrupts = <1>;
51 };
52
53 eeprom-wp {
54 label = "eeprom_wp";
55 linux,code = <BTN_3>;
56 interrupt-parent = <&gsc>;
57 interrupts = <2>;
58 };
59
60 tamper {
61 label = "tamper";
62 linux,code = <BTN_4>;
63 interrupt-parent = <&gsc>;
64 interrupts = <5>;
65 };
66
67 switch-hold {
68 label = "switch_hold";
69 linux,code = <BTN_5>;
70 interrupt-parent = <&gsc>;
71 interrupts = <7>;
72 };
73 };
74
75 leds {
76 compatible = "gpio-leds";
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_gpio_leds>;
79
80 led0: user1 {
81 label = "user1";
82 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
83 default-state = "on";
84 linux,default-trigger = "heartbeat";
85 };
86
87 led1: user2 {
88 label = "user2";
89 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
90 default-state = "off";
91 };
92
93 led2: user3 {
94 label = "user3";
95 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
96 default-state = "off";
97 };
98 };
99
100 pps {
101 compatible = "pps-gpio";
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_pps>;
104 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
105 status = "okay";
106 };
107
108 reg_3p3v: regulator-3p3v {
109 compatible = "regulator-fixed";
110 regulator-name = "3P3V";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 regulator-always-on;
114 };
115
116 reg_5p0v: regulator-5p0v {
117 compatible = "regulator-fixed";
118 regulator-name = "5P0V";
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 regulator-always-on;
122 };
123
124 reg_wl: regulator-wl {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_reg_wl>;
127 compatible = "regulator-fixed";
128 regulator-name = "wl";
129 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
130 startup-delay-us = <100>;
131 enable-active-high;
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 };
135};
136
137
138&ecspi3 {
139 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_ecspi3>;
142 status = "okay";
143};
144
145&fec {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_enet>;
148 phy-mode = "rgmii-id";
149 status = "okay";
150};
151
152&gpmi {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_gpmi_nand>;
155 status = "okay";
156};
157
158&i2c1 {
159 clock-frequency = <100000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c1>;
162 status = "okay";
163
164 gsc: gsc@20 {
165 compatible = "gw,gsc";
166 reg = <0x20>;
167 interrupt-parent = <&gpio1>;
168 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
171 #size-cells = <0>;
172
173 adc {
174 compatible = "gw,gsc-adc";
175 #address-cells = <1>;
176 #size-cells = <0>;
177
178 channel@6 {
179 gw,mode = <0>;
180 reg = <0x06>;
181 label = "temp";
182 };
183
184 channel@8 {
185 gw,mode = <3>;
186 reg = <0x08>;
187 label = "vdd_bat";
188 };
189
190 channel@82 {
191 gw,mode = <2>;
192 reg = <0x82>;
193 label = "vdd_vin";
194 gw,voltage-divider-ohms = <22100 1000>;
195 gw,voltage-offset-microvolt = <800000>;
196 };
197
198 channel@84 {
199 gw,mode = <2>;
200 reg = <0x84>;
201 label = "vdd_5p0";
202 gw,voltage-divider-ohms = <22100 10000>;
203 };
204
205 channel@86 {
206 gw,mode = <2>;
207 reg = <0x86>;
208 label = "vdd_3p3";
209 gw,voltage-divider-ohms = <10000 10000>;
210 };
211
212 channel@88 {
213 gw,mode = <2>;
214 reg = <0x88>;
215 label = "vdd_2p5";
216 gw,voltage-divider-ohms = <10000 10000>;
217 };
218
219 channel@8c {
220 gw,mode = <2>;
221 reg = <0x8c>;
222 label = "vdd_3p0";
223 };
224
225 channel@8e {
226 gw,mode = <2>;
227 reg = <0x8e>;
228 label = "vdd_arm";
229 };
230
231 channel@90 {
232 gw,mode = <2>;
233 reg = <0x90>;
234 label = "vdd_soc";
235 };
236
237 channel@92 {
238 gw,mode = <2>;
239 reg = <0x92>;
240 label = "vdd_1p5";
241 };
242
243 channel@98 {
244 gw,mode = <2>;
245 reg = <0x98>;
246 label = "vdd_1p8";
247 };
248
249 channel@9a {
250 gw,mode = <2>;
251 reg = <0x9a>;
252 label = "vdd_1p0";
253 gw,voltage-divider-ohms = <10000 10000>;
254 };
255
256 channel@9c {
257 gw,mode = <2>;
258 reg = <0x9c>;
259 label = "vdd_an1";
260 gw,voltage-divider-ohms = <10000 10000>;
261 };
262
263 channel@a2 {
264 gw,mode = <2>;
265 reg = <0xa2>;
266 label = "vdd_gsc";
267 gw,voltage-divider-ohms = <10000 10000>;
268 };
269 };
270 };
271
272 gsc_gpio: gpio@23 {
273 compatible = "nxp,pca9555";
274 reg = <0x23>;
275 gpio-controller;
276 #gpio-cells = <2>;
277 interrupt-parent = <&gsc>;
278 interrupts = <4>;
279 };
280
281 eeprom@50 {
282 compatible = "atmel,24c02";
283 reg = <0x50>;
284 pagesize = <16>;
285 };
286
287 eeprom@51 {
288 compatible = "atmel,24c02";
289 reg = <0x51>;
290 pagesize = <16>;
291 };
292
293 eeprom@52 {
294 compatible = "atmel,24c02";
295 reg = <0x52>;
296 pagesize = <16>;
297 };
298
299 eeprom@53 {
300 compatible = "atmel,24c02";
301 reg = <0x53>;
302 pagesize = <16>;
303 };
304
305 rtc@68 {
306 compatible = "dallas,ds1672";
307 reg = <0x68>;
308 };
309};
310
311&i2c2 {
312 clock-frequency = <100000>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_i2c2>;
315 status = "okay";
316};
317
318&i2c3 {
319 clock-frequency = <100000>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_i2c3>;
322 status = "okay";
323
324 accel@19 {
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_accel>;
327 compatible = "st,lis2de12";
328 reg = <0x19>;
329 st,drdy-int-pin = <1>;
330 interrupt-parent = <&gpio7>;
331 interrupts = <13 0>;
332 interrupt-names = "INT1";
333 };
334};
335
336&pcie {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_pcie>;
339 reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
340 status = "okay";
341};
342
343&pwm2 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
346 status = "disabled";
347};
348
349&pwm3 {
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
352 status = "disabled";
353};
354
355/* off-board RS232 */
356&uart1 {
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_uart1>;
359 status = "okay";
360};
361
362/* serial console */
363&uart2 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart2>;
366 status = "okay";
367};
368
369/* cc1352 */
370&uart3 {
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_uart3>;
373 uart-has-rtscts;
374 status = "okay";
375};
376
377/* Sterling-LWB Bluetooth */
378&uart4 {
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
381 uart-has-rtscts;
382 status = "okay";
383
384 bluetooth {
385 compatible = "brcm,bcm4330-bt";
386 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
387 };
388};
389
390/* GPS */
391&uart5 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_uart5>;
394 status = "okay";
395};
396
397&usbotg {
398 vbus-supply = <&reg_5p0v>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usbotg>;
401 disable-over-current;
Tim Harvey13acc632021-03-01 14:33:31 -0800[diff] [blame]402 dr_mode = "host";
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]403 status = "okay";
404};
405
406&usbh1 {
407 status = "okay";
408};
409
410/* Sterling-LWB SDIO WiFi */
411&usdhc2 {
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_usdhc2>;
414 vmmc-supply = <&reg_wl>;
415 non-removable;
416 bus-width = <4>;
417 status = "okay";
418};
419
420&usdhc3 {
421 pinctrl-names = "default", "state_100mhz", "state_200mhz";
422 pinctrl-0 = <&pinctrl_usdhc3>;
423 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
424 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
425 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
426 vmmc-supply = <&reg_3p3v>;
427 status = "okay";
428};
429
430&wdog1 {
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_wdog>;
433 fsl,ext-reset-output;
434};
435
436&iomuxc {
437 pinctrl_accel: accelmuxgrp {
438 fsl,pins = <
439 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
440 >;
441 };
442
443 pinctrl_bten: btengrp {
444 fsl,pins = <
445 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
446 >;
447 };
448
449 pinctrl_ecspi3: escpi3grp {
450 fsl,pins = <
451 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
452 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
453 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
454 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
455 >;
456 };
457
458 pinctrl_enet: enetgrp {
459 fsl,pins = <
460 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
461 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
462 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
463 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
464 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
465 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
466 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
467 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
468 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
469 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
470 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
471 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
472 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
473 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
474 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
475 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
476 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
477 >;
478 };
479
480 pinctrl_gpio_leds: gpioledsgrp {
481 fsl,pins = <
482 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
483 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
484 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
485 >;
486 };
487
488 pinctrl_gpmi_nand: gpminandgrp {
489 fsl,pins = <
490 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
491 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
492 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
493 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
494 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
495 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
496 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
497 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
498 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
499 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
500 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
501 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
502 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
503 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
504 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
505 >;
506 };
507
508 pinctrl_i2c1: i2c1grp {
509 fsl,pins = <
510 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
511 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
512 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
513 >;
514 };
515
516 pinctrl_i2c2: i2c2grp {
517 fsl,pins = <
518 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
519 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
520 >;
521 };
522
523 pinctrl_i2c3: i2c3grp {
524 fsl,pins = <
525 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
526 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
527 >;
528 };
529
530 pinctrl_pcie: pciegrp {
531 fsl,pins = <
532 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
533 >;
534 };
535
536 pinctrl_pps: ppsgrp {
537 fsl,pins = <
538 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
539 >;
540 };
541
542 pinctrl_pwm2: pwm2grp {
543 fsl,pins = <
544 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
545 >;
546 };
547
548 pinctrl_pwm3: pwm3grp {
549 fsl,pins = <
550 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
551 >;
552 };
553
554 pinctrl_reg_wl: regwlgrp {
555 fsl,pins = <
556 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
557 >;
558 };
559
560 pinctrl_uart1: uart1grp {
561 fsl,pins = <
562 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
563 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
564 >;
565 };
566
567 pinctrl_uart2: uart2grp {
568 fsl,pins = <
569 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
570 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
571 >;
572 };
573
574 pinctrl_uart3: uart3grp {
575 fsl,pins = <
576 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
577 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
578 MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
579 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
580 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
581 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
582 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
583 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
584 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
585 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
586 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
587 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
588 >;
589 };
590
591 pinctrl_uart4: uart4grp {
592 fsl,pins = <
593 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
594 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
595 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
596 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
597 >;
598 };
599
600 pinctrl_uart5: uart5grp {
601 fsl,pins = <
602 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
603 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
604 >;
605 };
606
607 pinctrl_usbotg: usbotggrp {
608 fsl,pins = <
609 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
610 >;
611 };
612
613 pinctrl_usdhc2: usdhc2grp {
614 fsl,pins = <
615 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
616 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
617 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
618 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
619 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
620 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
621 >;
622 };
623
624 pinctrl_usdhc3: usdhc3grp {
625 fsl,pins = <
626 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
627 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
628 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
629 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
630 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
631 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
632 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
633 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
634 >;
635 };
636
637 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
638 fsl,pins = <
639 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
640 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
641 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
642 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
643 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
644 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
645 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
646 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
647 >;
648 };
649
650 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
651 fsl,pins = <
652 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
653 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
654 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
655 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
656 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
657 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
658 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
659 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
660 >;
661 };
662
663 pinctrl_wdog: wdoggrp {
664 fsl,pins = <
665 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
666 >;
667 };
668};