Hans de Goede | 09f9510 | 2014-07-26 16:51:08 +0200 | [diff] [blame] | 1 | #include <common.h> |
| 2 | #include <asm/arch/dram.h> |
Hans de Goede | 8975cdf | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 3 | #include <linux/kconfig.h> |
Hans de Goede | 09f9510 | 2014-07-26 16:51:08 +0200 | [diff] [blame] | 4 | |
| 5 | static struct dram_para dram_para = { |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 6 | .clock = CONFIG_DRAM_CLK, |
Hans de Goede | 09f9510 | 2014-07-26 16:51:08 +0200 | [diff] [blame] | 7 | .type = 3, |
| 8 | .rank_num = 1, |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 9 | .density = 0, |
| 10 | .io_width = 0, |
| 11 | .bus_width = 0, |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 12 | .zq = CONFIG_DRAM_ZQ, |
Hans de Goede | 8975cdf | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 13 | .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 14 | .size = 0, |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 15 | #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC |
| 16 | .cas = 6, |
Hans de Goede | 09f9510 | 2014-07-26 16:51:08 +0200 | [diff] [blame] | 17 | .tpr0 = 0x30926692, |
| 18 | .tpr1 = 0x1090, |
| 19 | .tpr2 = 0x1a0c8, |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 20 | .emr2 = 0, |
| 21 | #else |
| 22 | # include "dram_timings_sun4i.h" |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 23 | .active_windowing = 1, |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 24 | #endif |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 25 | .tpr3 = CONFIG_DRAM_TPR3, |
Hans de Goede | 09f9510 | 2014-07-26 16:51:08 +0200 | [diff] [blame] | 26 | .tpr4 = 0, |
| 27 | .tpr5 = 0, |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 28 | .emr1 = CONFIG_DRAM_EMR1, |
Hans de Goede | 09f9510 | 2014-07-26 16:51:08 +0200 | [diff] [blame] | 29 | .emr3 = 0, |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 30 | .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, |
Hans de Goede | 09f9510 | 2014-07-26 16:51:08 +0200 | [diff] [blame] | 31 | }; |
| 32 | |
| 33 | unsigned long sunxi_dram_init(void) |
| 34 | { |
| 35 | return dramc_init(&dram_para); |
| 36 | } |