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Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00005 */
6
7/*
8 * BSC9132 QDS board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
harninder rai4aafbb42014-12-02 15:55:47 +053014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
16
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000017#ifdef CONFIG_BSC9132QDS
18#define CONFIG_BSC9132
19#endif
20
21#define CONFIG_MISC_INIT_R
22
23#ifdef CONFIG_SDCARD
24#define CONFIG_RAMBOOT_SDCARD
25#define CONFIG_SYS_RAMBOOT
26#define CONFIG_SYS_EXTRA_ENV_RELOC
27#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053028#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000029#endif
30#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
31#ifdef CONFIG_SPIFLASH
32#define CONFIG_RAMBOOT_SPIFLASH
33#define CONFIG_SYS_RAMBOOT
34#define CONFIG_SYS_EXTRA_ENV_RELOC
35#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053036#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000037#endif
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +053038#ifdef CONFIG_NAND_SECBOOT
39#define CONFIG_RAMBOOT_NAND
40#define CONFIG_SYS_RAMBOOT
41#define CONFIG_SYS_EXTRA_ENV_RELOC
42#define CONFIG_SYS_TEXT_BASE 0x11000000
43#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
44#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000045
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053046#ifdef CONFIG_NAND
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053047#define CONFIG_SPL_INIT_MINIMAL
48#define CONFIG_SPL_SERIAL_SUPPORT
49#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053050#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053051#define CONFIG_SPL_FLUSH_IMAGE
52#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
53
54#define CONFIG_SYS_TEXT_BASE 0x00201000
55#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
56#define CONFIG_SPL_MAX_SIZE 8192
57#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
58#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053059#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053060#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
61#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
62#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
63#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
64#endif
65
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000066#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053067#define CONFIG_SYS_TEXT_BASE 0x8ff40000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000068#endif
69
70#ifndef CONFIG_RESET_VECTOR_ADDRESS
71#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
72#endif
73
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053074#ifdef CONFIG_SPL_BUILD
75#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
76#else
77#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000078#endif
79
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000080/* High Level Configuration Options */
81#define CONFIG_BOOKE /* BOOKE */
82#define CONFIG_E500 /* BOOKE e500 family */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000083#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053084#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000085#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
86
87#define CONFIG_PCI /* Enable PCI/PCIE */
88#if defined(CONFIG_PCI)
89#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
90#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000091#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000092#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
93#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
94
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000095#define CONFIG_CMD_PCI
96
97#define CONFIG_E1000 /* E1000 pci Ethernet card*/
98
99/*
100 * PCI Windows
101 * Memory space is mapped 1-1, but I/O space must start from 0.
102 */
103/* controller 1, Slot 1, tgtid 1, Base address a000 */
104#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
105#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
106#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
107#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
108#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
109#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
110#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
111#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
112#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
113
114#define CONFIG_PCI_PNP /* do pci plug-and-play */
115
116#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
117#define CONFIG_DOS_PARTITION
118#endif
119
120#define CONFIG_FSL_LAW /* Use common FSL init code */
121#define CONFIG_ENV_OVERWRITE
122#define CONFIG_TSEC_ENET /* ethernet */
123
124#if defined(CONFIG_SYS_CLK_100_DDR_100)
125#define CONFIG_SYS_CLK_FREQ 100000000
126#define CONFIG_DDR_CLK_FREQ 100000000
127#elif defined(CONFIG_SYS_CLK_100_DDR_133)
128#define CONFIG_SYS_CLK_FREQ 100000000
129#define CONFIG_DDR_CLK_FREQ 133000000
130#endif
131
132#define CONFIG_MP
133
134#define CONFIG_HWCONFIG
135/*
136 * These can be toggled for performance analysis, otherwise use default.
137 */
138#define CONFIG_L2_CACHE /* toggle L2 cache */
139#define CONFIG_BTB /* enable branch predition */
140
141#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
142#define CONFIG_SYS_MEMTEST_END 0x01ffffff
143
144/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700145#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000146#define CONFIG_SYS_SPD_BUS_NUM 0
147#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
148#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
149#define CONFIG_FSL_DDR_INTERACTIVE
150
151#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
152
153#define CONFIG_SYS_SDRAM_SIZE (1024)
154#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
155#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
156
157#define CONFIG_DIMM_SLOTS_PER_CTLR 1
158
159/* DDR3 Controller Settings */
160#define CONFIG_CHIP_SELECTS_PER_CTRL 1
161#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
162#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
163#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
164#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
165#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
166#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
167#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
168#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
169#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
170
171#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
172#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
173#define CONFIG_SYS_DDR_RCW_1 0x00000000
174#define CONFIG_SYS_DDR_RCW_2 0x00000000
175#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
176#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
177#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
178#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
179
180#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
181#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
182#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
183#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
184
185#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
186#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
187#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
188#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
189#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
190#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
191#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
192#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
193#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
194
195#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
196#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
197#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
198#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
199#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
200#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
201#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
202#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
203#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
204
205/*FIXME: the following params are constant w.r.t diff freq
206combinations. this should be removed later
207*/
208#if CONFIG_DDR_CLK_FREQ == 100000000
209#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
210#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
211#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
212#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
213#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
214#elif CONFIG_DDR_CLK_FREQ == 133000000
215#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
216#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
217#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
218#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
219#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
220#else
221#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
222#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
223#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
224#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
225#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
226#endif
227
228
229/* relocated CCSRBAR */
230#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
231#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
232
233#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
234
Priyanka Jain64501c62013-07-02 09:21:04 +0530235/* DSP CCSRBAR */
236#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
237#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
238
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000239/*
240 * IFC Definitions
241 */
242/* NOR Flash on IFC */
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530243
244#ifdef CONFIG_SPL_BUILD
245#define CONFIG_SYS_NO_FLASH
246#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000247#define CONFIG_SYS_FLASH_BASE 0x88000000
248#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
249
250#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
251
252#define CONFIG_SYS_NOR_CSPR 0x88000101
253#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
254#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
255/* NOR Flash Timing Params */
256
257#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
258 | FTIM0_NOR_TEADC(0x03) \
259 | FTIM0_NOR_TAVDS(0x00) \
260 | FTIM0_NOR_TEAHC(0x0f))
261#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
262 | FTIM1_NOR_TRAD_NOR(0x09) \
263 | FTIM1_NOR_TSEQRAD_NOR(0x09))
264#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
265 | FTIM2_NOR_TCH(0x4) \
266 | FTIM2_NOR_TWPH(0x7) \
267 | FTIM2_NOR_TWP(0x1e))
268#define CONFIG_SYS_NOR_FTIM3 0x0
269
270#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
271#define CONFIG_SYS_FLASH_QUIET_TEST
272#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
273#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
274
275#undef CONFIG_SYS_FLASH_CHECKSUM
276#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
277#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
278
279/* CFI for NOR Flash */
280#define CONFIG_FLASH_CFI_DRIVER
281#define CONFIG_SYS_FLASH_CFI
282#define CONFIG_SYS_FLASH_EMPTY_INFO
283#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
284
285/* NAND Flash on IFC */
286#define CONFIG_SYS_NAND_BASE 0xff800000
287#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
288
289#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
290 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
291 | CSPR_MSEL_NAND /* MSEL = NAND */ \
292 | CSPR_V)
293#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
294
295#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
296 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
297 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
298 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
299 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
300 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
301 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
302
303/* NAND Flash Timing Params */
304#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
305 | FTIM0_NAND_TWP(0x05) \
306 | FTIM0_NAND_TWCHT(0x02) \
307 | FTIM0_NAND_TWH(0x04))
308#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
309 | FTIM1_NAND_TWBE(0x1e) \
310 | FTIM1_NAND_TRR(0x07) \
311 | FTIM1_NAND_TRP(0x05))
312#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
313 | FTIM2_NAND_TREH(0x04) \
314 | FTIM2_NAND_TWHRE(0x11))
315#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
316
317#define CONFIG_SYS_NAND_DDR_LAW 11
318
319/* NAND */
320#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
321#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000322#define CONFIG_CMD_NAND
323
324#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
325
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530326#ifndef CONFIG_SPL_BUILD
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000327#define CONFIG_FSL_QIXIS
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530328#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000329#ifdef CONFIG_FSL_QIXIS
330#define CONFIG_SYS_FPGA_BASE 0xffb00000
331#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
332#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
333#define QIXIS_LBMAP_SWITCH 9
334#define QIXIS_LBMAP_MASK 0x07
335#define QIXIS_LBMAP_SHIFT 0
336#define QIXIS_LBMAP_DFLTBANK 0x00
337#define QIXIS_LBMAP_ALTBANK 0x04
338#define QIXIS_RST_CTL_RESET 0x83
339#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
340#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
341#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
342
343#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
344
345#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
346 | CSPR_PORT_SIZE_8 \
347 | CSPR_MSEL_GPCM \
348 | CSPR_V)
349#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
350#define CONFIG_SYS_CSOR2 0x0
351/* CPLD Timing parameters for IFC CS3 */
352#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
353 FTIM0_GPCM_TEADC(0x0e) | \
354 FTIM0_GPCM_TEAHC(0x0e))
355#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
356 FTIM1_GPCM_TRAD(0x1f))
357#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800358 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000359 FTIM2_GPCM_TWP(0x1f))
360#define CONFIG_SYS_CS2_FTIM3 0x0
361#endif
362
363/* Set up IFC registers for boot location NOR/NAND */
Aneesh Bansal3051f3f2014-05-14 11:45:15 +0530364#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530365#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
366#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
367#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
368#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
369#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
370#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
371#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
372#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
373#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
374#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
375#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
376#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
377#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
378#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
379#else
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000380#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
381#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
382#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
383#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
384#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
385#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
386#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
387#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
388#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
389#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
390#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
391#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
392#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
393#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530394#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000395
396#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
397#define CONFIG_BOARD_EARLY_INIT_R
398
399#define CONFIG_SYS_INIT_RAM_LOCK
400#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
401#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
402
403#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
404 - GENERATED_GBL_DATA_SIZE)
405#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
406
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530407#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000408#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
409
410/* Serial Port */
411#define CONFIG_CONS_INDEX 1
412#undef CONFIG_SERIAL_SOFTWARE_FIFO
413#define CONFIG_SYS_NS16550
414#define CONFIG_SYS_NS16550_SERIAL
415#define CONFIG_SYS_NS16550_REG_SIZE 1
416#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530417#ifdef CONFIG_SPL_BUILD
418#define CONFIG_NS16550_MIN_FUNCTIONS
419#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000420
421#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
422#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
423
424#define CONFIG_SYS_BAUDRATE_TABLE \
425 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
426
427#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
428#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
429#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
430#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
431
432/* Use the HUSH parser */
433#define CONFIG_SYS_HUSH_PARSER /* hush parser */
434#ifdef CONFIG_SYS_HUSH_PARSER
435#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
436#endif
437
438/*
439 * Pass open firmware flat tree
440 */
441#define CONFIG_OF_LIBFDT
442#define CONFIG_OF_BOARD_SETUP
443#define CONFIG_OF_STDOUT_VIA_ALIAS
444
445/* new uImage format support */
446#define CONFIG_FIT
447#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
448
Heiko Schocher00f792e2012-10-24 13:48:22 +0200449#define CONFIG_SYS_I2C
450#define CONFIG_SYS_I2C_FSL
451#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
452#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
453#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
454#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
455#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
456#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000457
458/* I2C EEPROM */
459#define CONFIG_ID_EEPROM
460#ifdef CONFIG_ID_EEPROM
461#define CONFIG_SYS_I2C_EEPROM_NXID
462#endif
463#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
464#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
465#define CONFIG_SYS_EEPROM_BUS_NUM 0
466
467/* enable read and write access to EEPROM */
468#define CONFIG_CMD_EEPROM
469#define CONFIG_SYS_I2C_MULTI_EEPROMS
470#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
471#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
472#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
473
474/* I2C FPGA */
475#define CONFIG_I2C_FPGA
476#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
477
478#define CONFIG_RTC_DS3231
479#define CONFIG_SYS_I2C_RTC_ADDR 0x68
480
481/*
482 * SPI interface will not be available in case of NAND boot SPI CS0 will be
483 * used for SLIC
484 */
485/* eSPI - Enhanced SPI */
486#define CONFIG_FSL_ESPI /* SPI */
487#ifdef CONFIG_FSL_ESPI
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000488#define CONFIG_SPI_FLASH_SPANSION
489#define CONFIG_CMD_SF
490#define CONFIG_SF_DEFAULT_SPEED 10000000
491#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
492#endif
493
494#if defined(CONFIG_TSEC_ENET)
495
496#define CONFIG_MII /* MII PHY management */
497#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
498#define CONFIG_TSEC1 1
499#define CONFIG_TSEC1_NAME "eTSEC1"
500#define CONFIG_TSEC2 1
501#define CONFIG_TSEC2_NAME "eTSEC2"
502
503#define TSEC1_PHY_ADDR 0
504#define TSEC2_PHY_ADDR 1
505
506#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
507#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
508
509#define TSEC1_PHYIDX 0
510#define TSEC2_PHYIDX 0
511
512#define CONFIG_ETHPRIME "eTSEC1"
513
514#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
515
516/* TBI PHY configuration for SGMII mode */
517#define CONFIG_TSEC_TBICR_SETTINGS ( \
518 TBICR_PHY_RESET \
519 | TBICR_ANEG_ENABLE \
520 | TBICR_FULL_DUPLEX \
521 | TBICR_SPEED1_SET \
522 )
523
524#endif /* CONFIG_TSEC_ENET */
525
526#define CONFIG_MMC
527#ifdef CONFIG_MMC
528#define CONFIG_CMD_MMC
529#define CONFIG_DOS_PARTITION
530#define CONFIG_FSL_ESDHC
531#define CONFIG_GENERIC_MMC
532#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
533#endif
534
535#define CONFIG_USB_EHCI /* USB */
536#ifdef CONFIG_USB_EHCI
537#define CONFIG_CMD_USB
538#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
539#define CONFIG_USB_EHCI_FSL
540#define CONFIG_USB_STORAGE
541#define CONFIG_HAS_FSL_DR_USB
542#endif
543
544/*
545 * Environment
546 */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000547#if defined(CONFIG_RAMBOOT_SDCARD)
548#define CONFIG_ENV_IS_IN_MMC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530549#define CONFIG_FSL_FIXED_MMC_LOCATION
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000550#define CONFIG_SYS_MMC_ENV_DEV 0
551#define CONFIG_ENV_SIZE 0x2000
552#elif defined(CONFIG_RAMBOOT_SPIFLASH)
553#define CONFIG_ENV_IS_IN_SPI_FLASH
554#define CONFIG_ENV_SPI_BUS 0
555#define CONFIG_ENV_SPI_CS 0
556#define CONFIG_ENV_SPI_MAX_HZ 10000000
557#define CONFIG_ENV_SPI_MODE 0
558#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
559#define CONFIG_ENV_SECT_SIZE 0x10000
560#define CONFIG_ENV_SIZE 0x2000
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +0530561#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530562#define CONFIG_ENV_IS_IN_NAND
563#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530564#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530565#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
566#elif defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000567#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
568#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
569#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000570#else
571#define CONFIG_ENV_IS_IN_FLASH
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000572#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000573#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530574#define CONFIG_ENV_SECT_SIZE 0x20000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000575#endif
576
577#define CONFIG_LOADS_ECHO /* echo on for serial download */
578#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
579
580/*
581 * Command line configuration.
582 */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000583#define CONFIG_CMD_DATE
584#define CONFIG_CMD_DHCP
585#define CONFIG_CMD_ELF
586#define CONFIG_CMD_ERRATA
587#define CONFIG_CMD_I2C
588#define CONFIG_CMD_IRQ
589#define CONFIG_CMD_MII
590#define CONFIG_CMD_PING
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000591#define CONFIG_CMD_REGINFO
592
593#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
594#define CONFIG_CMD_EXT2
595#define CONFIG_CMD_FAT
596#define CONFIG_DOS_PARTITION
597#endif
598
Ruchika Gupta737537e2014-10-15 11:35:31 +0530599/* Hash command with SHA acceleration supported in hardware */
600#ifdef CONFIG_FSL_CAAM
601#define CONFIG_CMD_HASH
602#define CONFIG_SHA_HW_ACCEL
603#endif
604
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000605/*
606 * Miscellaneous configurable options
607 */
608#define CONFIG_SYS_LONGHELP /* undef to save memory */
609#define CONFIG_CMDLINE_EDITING /* Command-line editing */
610#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
611#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000612
613#if defined(CONFIG_CMD_KGDB)
614#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
615#else
616#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
617#endif
618#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
619 /* Print Buffer Size */
620#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
621#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000622
623
624/*
625 * For booting Linux, the board info and command line data
626 * have to be in the first 64 MB of memory, since this is
627 * the maximum mapped by the Linux kernel during initialization.
628 */
629#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
630#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
631
632#if defined(CONFIG_CMD_KGDB)
633#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000634#endif
635
636/*
Ashish Kumar42a9e2f2014-10-06 18:24:56 +0530637 * Dynamic MTD Partition support with mtdparts
638 */
639#ifndef CONFIG_SYS_NO_FLASH
640#define CONFIG_MTD_DEVICE
641#define CONFIG_MTD_PARTITIONS
642#define CONFIG_CMD_MTDPARTS
643#define CONFIG_FLASH_CFI_MTD
644#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
645#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
646 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
647 "8m(kernel),512k(dtb),-(fs)"
648#endif
649/*
650 * Override partitions in device tree using info
651 * in "mtdparts" environment variable
652 */
653#ifdef CONFIG_CMD_MTDPARTS
654#define CONFIG_FDT_FIXUP_PARTITIONS
655#endif
656
657/*
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000658 * Environment Configuration
659 */
660
661#if defined(CONFIG_TSEC_ENET)
662#define CONFIG_HAS_ETH0
663#define CONFIG_HAS_ETH1
664#endif
665
666#define CONFIG_HOSTNAME BSC9132qds
667#define CONFIG_ROOTPATH "/opt/nfsroot"
668#define CONFIG_BOOTFILE "uImage"
669#define CONFIG_UBOOTPATH "u-boot.bin"
670
671#define CONFIG_BAUDRATE 115200
harninder rai37811ec2014-12-15 12:58:45 +0530672#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000673
674#ifdef CONFIG_SDCARD
675#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
676#else
677#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
678#endif
679
680#define CONFIG_EXTRA_ENV_SETTINGS \
681 "netdev=eth0\0" \
682 "uboot=" CONFIG_UBOOTPATH "\0" \
683 "loadaddr=1000000\0" \
684 "bootfile=uImage\0" \
685 "consoledev=ttyS0\0" \
686 "ramdiskaddr=2000000\0" \
687 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
688 "fdtaddr=c00000\0" \
689 "fdtfile=bsc9132qds.dtb\0" \
690 "bdev=sda1\0" \
691 CONFIG_DEF_HWCONFIG\
692 "othbootargs=mem=880M ramdisk_size=600000 " \
693 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
694 "isolcpus=0\0" \
695 "usbext2boot=setenv bootargs root=/dev/ram rw " \
696 "console=$consoledev,$baudrate $othbootargs; " \
697 "usb start;" \
698 "ext2load usb 0:4 $loadaddr $bootfile;" \
699 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
700 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
701 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
702 "debug_halt_off=mw ff7e0e30 0xf0000000;"
703
704#define CONFIG_NFSBOOTCOMMAND \
705 "setenv bootargs root=/dev/nfs rw " \
706 "nfsroot=$serverip:$rootpath " \
707 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
708 "console=$consoledev,$baudrate $othbootargs;" \
709 "tftp $loadaddr $bootfile;" \
710 "tftp $fdtaddr $fdtfile;" \
711 "bootm $loadaddr - $fdtaddr"
712
713#define CONFIG_HDBOOT \
714 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
715 "console=$consoledev,$baudrate $othbootargs;" \
716 "usb start;" \
717 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
718 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
719 "bootm $loadaddr - $fdtaddr"
720
721#define CONFIG_RAMBOOTCOMMAND \
722 "setenv bootargs root=/dev/ram rw " \
723 "console=$consoledev,$baudrate $othbootargs; " \
724 "tftp $ramdiskaddr $ramdiskfile;" \
725 "tftp $loadaddr $bootfile;" \
726 "tftp $fdtaddr $fdtfile;" \
727 "bootm $loadaddr $ramdiskaddr $fdtaddr"
728
729#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
730
Aneesh Bansalf978f7c2014-03-12 00:07:27 +0530731#include <asm/fsl_secure_boot.h>
732
Ruchika Gupta789490b2014-10-07 15:48:46 +0530733#ifdef CONFIG_SECURE_BOOT
734#define CONFIG_CMD_BLOB
735#endif
736
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000737#endif /* __CONFIG_H */