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Sascha Hauercaebc952008-03-26 20:41:09 +01001/*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
6 *
Magnus Lilja70641222008-04-15 19:09:10 +02007 * Configuration settings for the LogicPD i.MX31 Litekit board.
Sascha Hauercaebc952008-03-26 20:41:09 +01008 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02009 * SPDX-License-Identifier: GPL-2.0+
Sascha Hauercaebc952008-03-26 20:41:09 +010010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Stefano Babic86271112011-03-14 15:43:56 +010015#include <asm/arch/imx-regs.h>
Magnus Liljae7ae84d2008-04-20 10:36:36 +020016
Sascha Hauercaebc952008-03-26 20:41:09 +010017 /* High Level Configuration Options */
Masahiro Yamada3fd968e2014-11-06 14:59:37 +090018#define CONFIG_MX31 1 /* This is a mx31 */
Sascha Hauercaebc952008-03-26 20:41:09 +010019#define CONFIG_MX31_CLK32 32000
20
21#define CONFIG_DISPLAY_CPUINFO
22#define CONFIG_DISPLAY_BOARDINFO
23
Fabio Estevamac88e662011-06-06 03:13:36 +000024#define CONFIG_SYS_TEXT_BASE 0xa0000000
25
Fabio Estevam4c414382011-09-22 08:07:17 +000026#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
27
Sascha Hauercaebc952008-03-26 20:41:09 +010028/* Temporarily disabled */
29#if 0
30#define CONFIG_OF_LIBFDT 1
31#define CONFIG_FIT 1
32#define CONFIG_FIT_VERBOSE 1
33#endif
34
35#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
36#define CONFIG_SETUP_MEMORY_TAGS 1
37#define CONFIG_INITRD_TAG 1
38
39/*
40 * Size of malloc() pool
41 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Sascha Hauercaebc952008-03-26 20:41:09 +010043
44/*
45 * Hardware drivers
46 */
47
Stefano Babic40f6fff2011-11-22 15:22:39 +010048#define CONFIG_MXC_UART
49#define CONFIG_MXC_UART_BASE UART1_BASE
Stefano Babic87e14f02011-08-26 11:54:05 +020050#define CONFIG_MXC_GPIO
Sascha Hauercaebc952008-03-26 20:41:09 +010051
Magnus Liljaf9204e12008-04-20 10:38:12 +020052#define CONFIG_HARD_SPI 1
53#define CONFIG_MXC_SPI 1
Haavard Skinnemoend255bb02008-05-16 11:10:31 +020054#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic9f481e92010-08-23 20:41:19 +020055#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Magnus Liljaf9204e12008-04-20 10:38:12 +020056
Stefano Babic2672d5d2011-10-08 11:01:52 +020057/* PMIC Controller */
Ɓukasz Majewskibe3b51a2012-11-13 03:22:14 +000058#define CONFIG_POWER
59#define CONFIG_POWER_SPI
60#define CONFIG_POWER_FSL
Stefano Babicdfe5e142010-04-16 17:11:19 +020061#define CONFIG_FSL_PMIC_BUS 1
62#define CONFIG_FSL_PMIC_CS 0
63#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic9f481e92010-08-23 20:41:19 +020064#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic2672d5d2011-10-08 11:01:52 +020065#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam4e8b7542011-10-24 06:44:15 +000066#define CONFIG_RTC_MC13XXX
Magnus Liljaf9204e12008-04-20 10:38:12 +020067
Sascha Hauercaebc952008-03-26 20:41:09 +010068/* allow to overwrite serial and ethaddr */
69#define CONFIG_ENV_OVERWRITE
70#define CONFIG_CONS_INDEX 1
71#define CONFIG_BAUDRATE 115200
Sascha Hauercaebc952008-03-26 20:41:09 +010072
73/***********************************************************
74 * Command definition
75 ***********************************************************/
Sascha Hauercaebc952008-03-26 20:41:09 +010076#define CONFIG_CMD_MII
77#define CONFIG_CMD_PING
Magnus Liljaf9204e12008-04-20 10:38:12 +020078#define CONFIG_CMD_SPI
79#define CONFIG_CMD_DATE
Magnus Liljaba6adeb2010-04-23 20:30:49 +020080#define CONFIG_CMD_NAND
Sascha Hauercaebc952008-03-26 20:41:09 +010081
82#define CONFIG_BOOTDELAY 3
83
84#define CONFIG_NETMASK 255.255.255.0
85#define CONFIG_IPADDR 192.168.23.168
86#define CONFIG_SERVERIP 192.168.23.2
87
88#define CONFIG_EXTRA_ENV_SETTINGS \
89 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
90 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
91 "bootcmd=run bootcmd_net\0" \
92 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
93 "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
94
95
Ben Warren736fead2009-07-20 22:01:11 -070096#define CONFIG_SMC911X 1
97#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
98#define CONFIG_SMC911X_32_BIT 1
Sascha Hauercaebc952008-03-26 20:41:09 +010099
100/*
101 * Miscellaneous configurable options
102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_LONGHELP /* undef to save memory */
104#define CONFIG_SYS_PROMPT "uboot> "
105#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sascha Hauercaebc952008-03-26 20:41:09 +0100106/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
108#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
109#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Sascha Hauercaebc952008-03-26 20:41:09 +0100110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
112#define CONFIG_SYS_MEMTEST_END 0x10000
Sascha Hauercaebc952008-03-26 20:41:09 +0100113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
Sascha Hauercaebc952008-03-26 20:41:09 +0100115
Sascha Hauercaebc952008-03-26 20:41:09 +0100116#define CONFIG_CMDLINE_EDITING 1
117
118/*-----------------------------------------------------------------------
Sascha Hauercaebc952008-03-26 20:41:09 +0100119 * Physical Memory Map
120 */
121#define CONFIG_NR_DRAM_BANKS 1
Magnus Liljae7ae84d2008-04-20 10:36:36 +0200122#define PHYS_SDRAM_1 CSD0_BASE
Sascha Hauercaebc952008-03-26 20:41:09 +0100123#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
Fabio Estevam4e377312011-06-05 14:56:02 +0000124#define CONFIG_BOARD_EARLY_INIT_F
Sascha Hauercaebc952008-03-26 20:41:09 +0100125
Fabio Estevam7a5faf02011-09-22 08:07:13 +0000126#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Magnus Lilja68a75d02010-10-16 19:47:06 +0200127#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200128#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200129#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Magnus Lilja68a75d02010-10-16 19:47:06 +0200130#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
131
Sascha Hauercaebc952008-03-26 20:41:09 +0100132/*-----------------------------------------------------------------------
133 * FLASH and environment organization
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_FLASH_BASE CS0_BASE
136#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
137#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
138#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
Sascha Hauercaebc952008-03-26 20:41:09 +0100139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200141#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_SECT_SIZE (64 * 1024)
143#define CONFIG_ENV_SIZE (64 * 1024)
Sascha Hauercaebc952008-03-26 20:41:09 +0100144
145/*-----------------------------------------------------------------------
146 * CFI FLASH driver setup
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200149#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
151#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Sascha Hauercaebc952008-03-26 20:41:09 +0100152
153/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
155#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Sascha Hauercaebc952008-03-26 20:41:09 +0100156
157/*
158 * JFFS2 partitions
159 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100160#undef CONFIG_CMD_MTDPARTS
Sascha Hauercaebc952008-03-26 20:41:09 +0100161#define CONFIG_JFFS2_DEV "nor0"
162
Magnus Liljaba6adeb2010-04-23 20:30:49 +0200163/*
164 * NAND flash
165 */
166#define CONFIG_NAND_MXC
167#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
168#define CONFIG_SYS_MAX_NAND_DEVICE 1
169#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
170#define CONFIG_MXC_NAND_HWECC
171
Sascha Hauercaebc952008-03-26 20:41:09 +0100172#endif /* __CONFIG_H */