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Heiko Schocher4ce5a722009-07-20 09:59:37 +02001/*
Albert Aribaud306563a2010-08-27 18:26:05 +02002 * Driver for the TWSI (i2c) controller found on the Marvell
3 * orion5x and kirkwood SoC families.
Heiko Schocher4ce5a722009-07-20 09:59:37 +02004 *
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02005 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
Albert Aribaud306563a2010-08-27 18:26:05 +02006 * Copyright (c) 2010 Albert Aribaud.
Heiko Schocher4ce5a722009-07-20 09:59:37 +02007 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher4ce5a722009-07-20 09:59:37 +02009 */
Albert Aribaud306563a2010-08-27 18:26:05 +020010
Heiko Schocher4ce5a722009-07-20 09:59:37 +020011#include <common.h>
12#include <i2c.h>
Heiko Schocher4ce5a722009-07-20 09:59:37 +020013#include <asm/errno.h>
14#include <asm/io.h>
15
Heiko Schocher4ce5a722009-07-20 09:59:37 +020016/*
Albert Aribaud306563a2010-08-27 18:26:05 +020017 * include a file that will provide CONFIG_I2C_MVTWSI_BASE
18 * and possibly other settings
Heiko Schocher4ce5a722009-07-20 09:59:37 +020019 */
20
Albert Aribaud306563a2010-08-27 18:26:05 +020021#if defined(CONFIG_ORION5X)
22#include <asm/arch/orion5x.h>
Stefan Roese6d5fe562014-10-22 12:13:16 +020023#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP))
Stefan Roese3dc23f72014-10-22 12:13:06 +020024#include <asm/arch/soc.h>
Hans de Goede66203772014-06-13 22:55:49 +020025#elif defined(CONFIG_SUNXI)
26#include <asm/arch/i2c.h>
Albert Aribaud306563a2010-08-27 18:26:05 +020027#else
28#error Driver mvtwsi not supported by SoC or board
29#endif
30
31/*
32 * TWSI register structure
33 */
34
Hans de Goede66203772014-06-13 22:55:49 +020035#ifdef CONFIG_SUNXI
36
37struct mvtwsi_registers {
38 u32 slave_address;
39 u32 xtnd_slave_addr;
40 u32 data;
41 u32 control;
42 u32 status;
43 u32 baudrate;
44 u32 soft_reset;
45};
46
47#else
48
Albert Aribaud306563a2010-08-27 18:26:05 +020049struct mvtwsi_registers {
50 u32 slave_address;
51 u32 data;
52 u32 control;
53 union {
54 u32 status; /* when reading */
55 u32 baudrate; /* when writing */
56 };
57 u32 xtnd_slave_addr;
58 u32 reserved[2];
59 u32 soft_reset;
60};
61
Hans de Goede66203772014-06-13 22:55:49 +020062#endif
63
Albert Aribaud306563a2010-08-27 18:26:05 +020064/*
65 * Control register fields
66 */
67
68#define MVTWSI_CONTROL_ACK 0x00000004
69#define MVTWSI_CONTROL_IFLG 0x00000008
70#define MVTWSI_CONTROL_STOP 0x00000010
71#define MVTWSI_CONTROL_START 0x00000020
72#define MVTWSI_CONTROL_TWSIEN 0x00000040
73#define MVTWSI_CONTROL_INTEN 0x00000080
74
75/*
76 * Status register values -- only those expected in normal master
77 * operation on non-10-bit-address devices; whatever status we don't
78 * expect in nominal conditions (bus errors, arbitration losses,
79 * missing ACKs...) we just pass back to the caller as an error
80 * code.
81 */
82
83#define MVTWSI_STATUS_START 0x08
84#define MVTWSI_STATUS_REPEATED_START 0x10
85#define MVTWSI_STATUS_ADDR_W_ACK 0x18
86#define MVTWSI_STATUS_DATA_W_ACK 0x28
87#define MVTWSI_STATUS_ADDR_R_ACK 0x40
88#define MVTWSI_STATUS_ADDR_R_NAK 0x48
89#define MVTWSI_STATUS_DATA_R_ACK 0x50
90#define MVTWSI_STATUS_DATA_R_NAK 0x58
91#define MVTWSI_STATUS_IDLE 0xF8
92
93/*
94 * The single instance of the controller we'll be dealing with
95 */
96
97static struct mvtwsi_registers *twsi =
98 (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE;
99
100/*
101 * Returned statuses are 0 for success and nonzero otherwise.
102 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
103 * Thus to ease debugging, the return status contains some debug info:
104 * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
105 * - bits 23..16 are the last value of the control register.
106 * - bits 15..8 are the last value of the status register.
107 * - bits 7..0 are the expected value of the status register.
108 */
109
110#define MVTWSI_ERROR_WRONG_STATUS 0x01
111#define MVTWSI_ERROR_TIMEOUT 0x02
112
113#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \
114 ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF))
115
116/*
117 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
118 * return 0 (ok) or return 'wrong status'.
119 */
120static int twsi_wait(int expected_status)
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200121{
Albert Aribaud306563a2010-08-27 18:26:05 +0200122 int control, status;
123 int timeout = 1000;
124
125 do {
126 control = readl(&twsi->control);
127 if (control & MVTWSI_CONTROL_IFLG) {
128 status = readl(&twsi->status);
129 if (status == expected_status)
130 return 0;
131 else
132 return MVTWSI_ERROR(
133 MVTWSI_ERROR_WRONG_STATUS,
134 control, status, expected_status);
135 }
136 udelay(10); /* one clock cycle at 100 kHz */
137 } while (timeout--);
138 status = readl(&twsi->status);
139 return MVTWSI_ERROR(
140 MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200141}
142
Albert Aribaud306563a2010-08-27 18:26:05 +0200143/*
144 * These flags are ORed to any write to the control register
145 * They allow global setting of TWSIEN and ACK.
146 * By default none are set.
147 * twsi_start() sets TWSIEN (in case the controller was disabled)
148 * twsi_recv() sets ACK or resets it depending on expected status.
149 */
150static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200151
Albert Aribaud306563a2010-08-27 18:26:05 +0200152/*
153 * Assert the START condition, either in a single I2C transaction
154 * or inside back-to-back ones (repeated starts).
155 */
156static int twsi_start(int expected_status)
157{
158 /* globally set TWSIEN in case it was not */
159 twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
160 /* assert START */
161 writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
162 /* wait for controller to process START */
163 return twsi_wait(expected_status);
164}
165
166/*
167 * Send a byte (i2c address or data).
168 */
169static int twsi_send(u8 byte, int expected_status)
170{
171 /* put byte in data register for sending */
172 writel(byte, &twsi->data);
173 /* clear any pending interrupt -- that'll cause sending */
174 writel(twsi_control_flags, &twsi->control);
175 /* wait for controller to receive byte and check ACK */
176 return twsi_wait(expected_status);
177}
178
179/*
180 * Receive a byte.
181 * Global mvtwsi_control_flags variable says if we should ack or nak.
182 */
183static int twsi_recv(u8 *byte)
184{
185 int expected_status, status;
186
187 /* compute expected status based on ACK bit in global control flags */
188 if (twsi_control_flags & MVTWSI_CONTROL_ACK)
189 expected_status = MVTWSI_STATUS_DATA_R_ACK;
190 else
191 expected_status = MVTWSI_STATUS_DATA_R_NAK;
192 /* acknowledge *previous state* and launch receive */
193 writel(twsi_control_flags, &twsi->control);
194 /* wait for controller to receive byte and assert ACK or NAK */
195 status = twsi_wait(expected_status);
196 /* if we did receive expected byte then store it */
197 if (status == 0)
198 *byte = readl(&twsi->data);
199 /* return status */
200 return status;
201}
202
203/*
204 * Assert the STOP condition.
205 * This is also used to force the bus back in idle (SDA=SCL=1).
206 */
207static int twsi_stop(int status)
208{
209 int control, stop_status;
210 int timeout = 1000;
211
212 /* assert STOP */
213 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
214 writel(control, &twsi->control);
215 /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
216 do {
217 stop_status = readl(&twsi->status);
218 if (stop_status == MVTWSI_STATUS_IDLE)
219 break;
220 udelay(10); /* one clock cycle at 100 kHz */
221 } while (timeout--);
222 control = readl(&twsi->control);
223 if (stop_status != MVTWSI_STATUS_IDLE)
224 if (status == 0)
225 status = MVTWSI_ERROR(
226 MVTWSI_ERROR_TIMEOUT,
227 control, status, MVTWSI_STATUS_IDLE);
228 return status;
229}
230
231/*
232 * Ugly formula to convert m and n values to a frequency comes from
233 * TWSI specifications
234 */
235
236#define TWSI_FREQUENCY(m, n) \
Hans de Goedefab356a2014-05-03 17:46:26 +0200237 (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
Albert Aribaud306563a2010-08-27 18:26:05 +0200238
239/*
Albert Aribaud306563a2010-08-27 18:26:05 +0200240 * Reset controller.
Albert Aribaud306563a2010-08-27 18:26:05 +0200241 * Controller reset also resets the baud rate and slave address, so
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200242 * they must be re-established afterwards.
Albert Aribaud306563a2010-08-27 18:26:05 +0200243 */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200244static void twsi_reset(struct i2c_adapter *adap)
Albert Aribaud306563a2010-08-27 18:26:05 +0200245{
246 /* ensure controller will be enabled by any twsi*() function */
247 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
248 /* reset controller */
249 writel(0, &twsi->soft_reset);
250 /* wait 2 ms -- this is what the Marvell LSP does */
251 udelay(20000);
Albert Aribaud306563a2010-08-27 18:26:05 +0200252}
253
254/*
255 * I2C init called by cmd_i2c when doing 'i2c reset'.
256 * Sets baud to the highest possible value not exceeding requested one.
257 */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200258static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
259 unsigned int requested_speed)
Albert Aribaud306563a2010-08-27 18:26:05 +0200260{
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200261 unsigned int tmp_speed, highest_speed, n, m;
262 unsigned int baud = 0x44; /* baudrate at controller reset */
Albert Aribaud306563a2010-08-27 18:26:05 +0200263
264 /* use actual speed to collect progressively higher values */
265 highest_speed = 0;
266 /* compute m, n setting for highest speed not above requested speed */
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200267 for (n = 0; n < 8; n++) {
268 for (m = 0; m < 16; m++) {
Albert Aribaud306563a2010-08-27 18:26:05 +0200269 tmp_speed = TWSI_FREQUENCY(m, n);
270 if ((tmp_speed <= requested_speed)
271 && (tmp_speed > highest_speed)) {
272 highest_speed = tmp_speed;
273 baud = (m << 3) | n;
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200274 }
275 }
276 }
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200277 writel(baud, &twsi->baudrate);
278 return 0;
279}
280
281static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
282{
Albert Aribaud306563a2010-08-27 18:26:05 +0200283 /* reset controller */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200284 twsi_reset(adap);
285 /* set speed */
286 twsi_i2c_set_bus_speed(adap, speed);
287 /* set slave address even though we don't use it */
288 writel(slaveadd, &twsi->slave_address);
289 writel(0, &twsi->xtnd_slave_addr);
290 /* assert STOP but don't care for the result */
291 (void) twsi_stop(0);
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200292}
293
Albert Aribaud306563a2010-08-27 18:26:05 +0200294/*
295 * Begin I2C transaction with expected start status, at given address.
296 * Common to i2c_probe, i2c_read and i2c_write.
297 * Expected address status will derive from direction bit (bit 0) in addr.
298 */
299static int i2c_begin(int expected_start_status, u8 addr)
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200300{
Albert Aribaud306563a2010-08-27 18:26:05 +0200301 int status, expected_addr_status;
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200302
Albert Aribaud306563a2010-08-27 18:26:05 +0200303 /* compute expected address status from direction bit in addr */
304 if (addr & 1) /* reading */
305 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
306 else /* writing */
307 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
308 /* assert START */
309 status = twsi_start(expected_start_status);
310 /* send out the address if the start went well */
311 if (status == 0)
312 status = twsi_send(addr, expected_addr_status);
313 /* return ok or status of first failure to caller */
314 return status;
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200315}
316
Albert Aribaud306563a2010-08-27 18:26:05 +0200317/*
318 * I2C probe called by cmd_i2c when doing 'i2c probe'.
319 * Begin read, nak data byte, end.
320 */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200321static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200322{
Albert Aribaud306563a2010-08-27 18:26:05 +0200323 u8 dummy_byte;
324 int status;
325
326 /* begin i2c read */
327 status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1);
328 /* dummy read was accepted: receive byte but NAK it. */
329 if (status == 0)
330 status = twsi_recv(&dummy_byte);
331 /* Stop transaction */
332 twsi_stop(0);
333 /* return 0 or status of first failure */
334 return status;
335}
336
337/*
338 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
339 * Begin write, send address byte(s), begin read, receive data bytes, end.
340 *
341 * NOTE: some EEPROMS want a stop right before the second start, while
342 * some will choke if it is there. Deciding which we should do is eeprom
343 * stuff, not i2c, but at the moment the APIs won't let us put it in
344 * cmd_eeprom, so we have to choose here, and for the moment that'll be
345 * a repeated start without a preceding stop.
346 */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200347static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
348 int alen, uchar *data, int length)
Albert Aribaud306563a2010-08-27 18:26:05 +0200349{
350 int status;
351
352 /* begin i2c write to send the address bytes */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200353 status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
Albert Aribaud306563a2010-08-27 18:26:05 +0200354 /* send addr bytes */
355 while ((status == 0) && alen--)
356 status = twsi_send(addr >> (8*alen),
357 MVTWSI_STATUS_DATA_W_ACK);
358 /* begin i2c read to receive eeprom data bytes */
359 if (status == 0)
360 status = i2c_begin(
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200361 MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1);
Albert Aribaud306563a2010-08-27 18:26:05 +0200362 /* prepare ACK if at least one byte must be received */
363 if (length > 0)
364 twsi_control_flags |= MVTWSI_CONTROL_ACK;
365 /* now receive actual bytes */
366 while ((status == 0) && length--) {
367 /* reset NAK if we if no more to read now */
368 if (length == 0)
369 twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
370 /* read current byte */
371 status = twsi_recv(data++);
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200372 }
Albert Aribaud306563a2010-08-27 18:26:05 +0200373 /* Stop transaction */
374 status = twsi_stop(status);
375 /* return 0 or status of first failure */
376 return status;
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200377}
378
Albert Aribaud306563a2010-08-27 18:26:05 +0200379/*
380 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
381 * Begin write, send address byte(s), send data bytes, end.
382 */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200383static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
384 int alen, uchar *data, int length)
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200385{
Albert Aribaud306563a2010-08-27 18:26:05 +0200386 int status;
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200387
Albert Aribaud306563a2010-08-27 18:26:05 +0200388 /* begin i2c write to send the eeprom adress bytes then data bytes */
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200389 status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
Albert Aribaud306563a2010-08-27 18:26:05 +0200390 /* send addr bytes */
391 while ((status == 0) && alen--)
392 status = twsi_send(addr >> (8*alen),
393 MVTWSI_STATUS_DATA_W_ACK);
394 /* send data bytes */
395 while ((status == 0) && (length-- > 0))
396 status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK);
397 /* Stop transaction */
398 status = twsi_stop(status);
399 /* return 0 or status of first failure */
400 return status;
Heiko Schocher4ce5a722009-07-20 09:59:37 +0200401}
402
Hans de Goede0db2bbd2014-06-13 22:55:48 +0200403U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
404 twsi_i2c_read, twsi_i2c_write,
405 twsi_i2c_set_bus_speed,
406 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)