blob: 8ed0f7c21afee03ee22fb1ab50c4e93860a8cf6e [file] [log] [blame]
Kim Phillips5e918a92008-01-16 00:38:05 -06001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Kim Phillips5e918a92008-01-16 00:38:05 -06007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050016#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Kim Phillips5e918a92008-01-16 00:38:05 -060017#define CONFIG_MPC837XERDB 1
18
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019#define CONFIG_SYS_TEXT_BASE 0xFE000000
20
Kim Phillips5e918a92008-01-16 00:38:05 -060021#define CONFIG_PCI 1
22
Anton Vorontsov2bd74602008-03-24 17:40:43 +030023#define CONFIG_BOARD_EARLY_INIT_F
Timur Tabi89c77842008-02-08 13:15:55 -060024#define CONFIG_MISC_INIT_R
Anton Vorontsovc9646ed2009-06-10 00:25:30 +040025#define CONFIG_HWCONFIG
Timur Tabi89c77842008-02-08 13:15:55 -060026
27/*
28 * On-board devices
29 */
30#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
31#define CONFIG_VSC7385_ENET
32
Kim Phillips5e918a92008-01-16 00:38:05 -060033/*
34 * System Clock Setup
35 */
36#ifdef CONFIG_PCISLAVE
37#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
38#else
39#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Kim Phillipsbe9b56d2009-07-23 14:09:38 -050040#define CONFIG_PCIE
Kim Phillips5e918a92008-01-16 00:38:05 -060041#endif
42
43#ifndef CONFIG_SYS_CLK_FREQ
44#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
45#endif
46
47/*
48 * Hardware Reset Configuration Word
49 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips5e918a92008-01-16 00:38:05 -060051 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 HRCWL_DDR_TO_SCB_CLK_1X1 |\
53 HRCWL_SVCOD_DIV_2 |\
54 HRCWL_CSB_TO_CLKIN_5X1 |\
55 HRCWL_CORE_TO_CSB_2X1)
56
57#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060059 HRCWH_PCI_AGENT |\
60 HRCWH_PCI1_ARBITER_DISABLE |\
61 HRCWH_CORE_ENABLE |\
62 HRCWH_FROM_0XFFF00100 |\
63 HRCWH_BOOTSEQ_DISABLE |\
64 HRCWH_SW_WATCHDOG_DISABLE |\
65 HRCWH_ROM_LOC_LOCAL_16BIT |\
66 HRCWH_RL_EXT_LEGACY |\
67 HRCWH_TSEC1M_IN_RGMII |\
68 HRCWH_TSEC2M_IN_RGMII |\
69 HRCWH_BIG_ENDIAN |\
70 HRCWH_LDP_CLEAR)
71#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060073 HRCWH_PCI_HOST |\
74 HRCWH_PCI1_ARBITER_ENABLE |\
75 HRCWH_CORE_ENABLE |\
76 HRCWH_FROM_0X00000100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY |\
81 HRCWH_TSEC1M_IN_RGMII |\
82 HRCWH_TSEC2M_IN_RGMII |\
83 HRCWH_BIG_ENDIAN |\
84 HRCWH_LDP_CLEAR)
85#endif
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087/* System performance - define the value i.e. CONFIG_SYS_XXX
Kim Phillips5e918a92008-01-16 00:38:05 -060088*/
89
90/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger5afe9722011-10-11 23:57:19 -050092#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Kim Phillips5e918a92008-01-16 00:38:05 -060093
94/* System Priority Control Regsiter */
Joe Hershberger5afe9722011-10-11 23:57:19 -050095#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -060096
97/* System Clock Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
99#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500100#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600101
102/*
103 * System IO Config
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_SICRH 0x08200000
106#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600107
108/*
109 * Output Buffer Impedance
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_OBIR 0x30100000
Kim Phillips5e918a92008-01-16 00:38:05 -0600112
113/*
114 * IMMR new address
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600117
118/*
Timur Tabi89c77842008-02-08 13:15:55 -0600119 * Device configurations
120 */
121
122/* Vitesse 7385 */
123
124#ifdef CONFIG_VSC7385_ENET
125
126#define CONFIG_TSEC2
127
128/* The flash address and size of the VSC7385 firmware image */
129#define CONFIG_VSC7385_IMAGE 0xFE7FE000
130#define CONFIG_VSC7385_IMAGE_SIZE 8192
131
132#endif
133
134/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600135 * DDR Setup
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
138#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
139#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
140#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
141#define CONFIG_SYS_83XX_DDR_USES_CS0
Kim Phillips5e918a92008-01-16 00:38:05 -0600142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
Kim Phillips5e918a92008-01-16 00:38:05 -0600144
145#undef CONFIG_DDR_ECC /* support DDR ECC function */
146#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
147
148#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
149
150/*
151 * Manually set up DDR parameters
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500154#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
155#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
156 | CSCONFIG_ODT_WR_ONLY_CURRENT \
157 | CSCONFIG_ROW_BIT_13 \
158 | CSCONFIG_COL_BIT_10)
Kim Phillips5e918a92008-01-16 00:38:05 -0600159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_DDR_TIMING_3 0x00000000
161#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600162 | (0 << TIMING_CFG0_WRT_SHIFT) \
163 | (0 << TIMING_CFG0_RRT_SHIFT) \
164 | (0 << TIMING_CFG0_WWT_SHIFT) \
165 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
166 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
167 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
168 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600169 /* 0x00260802 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600171 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
172 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
173 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
174 | (13 << TIMING_CFG1_REFREC_SHIFT) \
175 | (3 << TIMING_CFG1_WRREC_SHIFT) \
176 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
177 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600178 /* 0x3937d322 */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500179#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
180 | (5 << TIMING_CFG2_CPO_SHIFT) \
181 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
182 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
183 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
184 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
185 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
186 /* 0x02984cc8 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600187
Kim Phillips8eceeb72009-08-21 16:33:15 -0500188#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
189 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600190 /* 0x06090100 */
191
192#if defined(CONFIG_DDR_2T_TIMING)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500193#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500194 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
195 | SDRAM_CFG_32_BE \
196 | SDRAM_CFG_2T_EN)
197 /* 0x43088000 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600198#else
Joe Hershberger5afe9722011-10-11 23:57:19 -0500199#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500200 | SDRAM_CFG_SDRAM_TYPE_DDR2)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500201 /* 0x43000000 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600202#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Kim Phillips8eceeb72009-08-21 16:33:15 -0500204#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500205 | (0x0442 << SDRAM_MODE_SD_SHIFT))
206 /* 0x04400442 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_DDR_MODE2 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600208
209/*
210 * Memory test
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
213#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
214#define CONFIG_SYS_MEMTEST_END 0x0ef70010
Kim Phillips5e918a92008-01-16 00:38:05 -0600215
216/*
217 * The reserved memory
218 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200219#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips5e918a92008-01-16 00:38:05 -0600220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
222#define CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600223#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#undef CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600225#endif
226
Joe Hershberger5afe9722011-10-11 23:57:19 -0500227#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
228#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Kim Phillips5e918a92008-01-16 00:38:05 -0600229
230/*
231 * Initial RAM Base Address Setup
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_RAM_LOCK 1
234#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200235#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500236#define CONFIG_SYS_GBL_DATA_OFFSET \
237 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips5e918a92008-01-16 00:38:05 -0600238
239/*
240 * Local Bus Configuration & Clock Setup
241 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500242#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
243#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500245#define CONFIG_FSL_ELBC 1
Kim Phillips5e918a92008-01-16 00:38:05 -0600246
247/*
248 * FLASH on the Local Bus
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200251#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
253#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600254
Joe Hershberger5afe9722011-10-11 23:57:19 -0500255#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
256#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
257#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Kim Phillips5e918a92008-01-16 00:38:05 -0600258
Joe Hershberger5afe9722011-10-11 23:57:19 -0500259 /* Window base at flash base */
260#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600262
Joe Hershberger5afe9722011-10-11 23:57:19 -0500263#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500264 | BR_PS_16 /* 16 bit port */ \
265 | BR_MS_GPCM /* MSEL = GPCM */ \
266 | BR_V) /* valid */
267#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600268 | OR_GPCM_XACS \
269 | OR_GPCM_SCY_9 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500270 | OR_GPCM_EHTR_SET \
Kim Phillips5e918a92008-01-16 00:38:05 -0600271 | OR_GPCM_EAD)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500272 /* 0xFF800191 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
275#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Kim Phillips5e918a92008-01-16 00:38:05 -0600276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#undef CONFIG_SYS_FLASH_CHECKSUM
278#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
279#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600280
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300281/*
282 * NAND Flash on the Local Bus
283 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500284#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500285#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500286 | BR_DECC_CHK_GEN /* Use HW ECC */ \
287 | BR_PS_8 /* 8 bit port */ \
288 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500289 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500290#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500291 | OR_FCM_CSCT \
292 | OR_FCM_CST \
293 | OR_FCM_CHT \
294 | OR_FCM_SCY_1 \
295 | OR_FCM_TRLX \
296 | OR_FCM_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500298#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300299
Timur Tabi89c77842008-02-08 13:15:55 -0600300/* Vitesse 7385 */
301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_VSC7385_BASE 0xF0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600303
Timur Tabi89c77842008-02-08 13:15:55 -0600304#ifdef CONFIG_VSC7385_ENET
305
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500306#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
307 | BR_PS_8 \
308 | BR_MS_GPCM \
309 | BR_V)
310 /* 0xF0000801 */
311#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
312 | OR_GPCM_CSNT \
313 | OR_GPCM_XACS \
314 | OR_GPCM_SCY_15 \
315 | OR_GPCM_SETA \
316 | OR_GPCM_TRLX_SET \
317 | OR_GPCM_EHTR_SET \
318 | OR_GPCM_EAD)
319 /* 0xfffe09ff */
320
Joe Hershberger5afe9722011-10-11 23:57:19 -0500321 /* Access Base */
322#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500323#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Kim Phillips5e918a92008-01-16 00:38:05 -0600324
Timur Tabi89c77842008-02-08 13:15:55 -0600325#endif
326
Kim Phillips5e918a92008-01-16 00:38:05 -0600327/*
328 * Serial Port
329 */
330#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_NS16550
332#define CONFIG_SYS_NS16550_SERIAL
333#define CONFIG_SYS_NS16550_REG_SIZE 1
334#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips5e918a92008-01-16 00:38:05 -0600335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Kim Phillips5e918a92008-01-16 00:38:05 -0600338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
340#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips5e918a92008-01-16 00:38:05 -0600341
Anton Vorontsov2bd74602008-03-24 17:40:43 +0300342/* SERDES */
343#define CONFIG_FSL_SERDES
344#define CONFIG_FSL_SERDES1 0xe3000
345#define CONFIG_FSL_SERDES2 0xe3100
346
Kim Phillips5e918a92008-01-16 00:38:05 -0600347/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_HUSH_PARSER
Kim Phillips5e918a92008-01-16 00:38:05 -0600349
350/* Pass open firmware flat tree */
351#define CONFIG_OF_LIBFDT 1
352#define CONFIG_OF_BOARD_SETUP 1
Anton Vorontsovaabce7f2008-03-24 17:40:47 +0300353#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillips5e918a92008-01-16 00:38:05 -0600354
355/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200356#define CONFIG_SYS_I2C
357#define CONFIG_SYS_I2C_FSL
358#define CONFIG_SYS_FSL_I2C_SPEED 400000
359#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
360#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
361#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Kim Phillips5e918a92008-01-16 00:38:05 -0600362
363/*
364 * Config on-board RTC
365 */
366#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600368
369/*
370 * General PCI
371 * Addresses are mapped 1-1.
372 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500373#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
374#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
375#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
377#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
378#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
379#define CONFIG_SYS_PCI_IO_BASE 0x00000000
380#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
381#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
384#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
385#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600386
Anton Vorontsov7e915582009-02-19 18:20:52 +0300387#define CONFIG_SYS_PCIE1_BASE 0xA0000000
388#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
389#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
390#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
391#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
392#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
393#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
394#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
395#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
396
397#define CONFIG_SYS_PCIE2_BASE 0xC0000000
398#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
399#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
400#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
401#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
402#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
403#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
404#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
405#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
406
Kim Phillips5e918a92008-01-16 00:38:05 -0600407#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000408#define CONFIG_PCI_INDIRECT_BRIDGE
Kim Phillips5e918a92008-01-16 00:38:05 -0600409#define CONFIG_PCI_PNP /* do pci plug-and-play */
410
Kim Phillips5e918a92008-01-16 00:38:05 -0600411#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips5e918a92008-01-16 00:38:05 -0600413#endif /* CONFIG_PCI */
414
Kim Phillips5e918a92008-01-16 00:38:05 -0600415/*
416 * TSEC
417 */
Timur Tabi89c77842008-02-08 13:15:55 -0600418#ifdef CONFIG_TSEC_ENET
Kim Phillips5e918a92008-01-16 00:38:05 -0600419
Timur Tabi89c77842008-02-08 13:15:55 -0600420#define CONFIG_GMII /* MII PHY management */
421
422#define CONFIG_TSEC1
423
424#ifdef CONFIG_TSEC1
425#define CONFIG_HAS_ETH0
Kim Phillips5e918a92008-01-16 00:38:05 -0600426#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Kim Phillips5e918a92008-01-16 00:38:05 -0600428#define TSEC1_PHY_ADDR 2
Kim Phillips5e918a92008-01-16 00:38:05 -0600429#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Kim Phillips5e918a92008-01-16 00:38:05 -0600430#define TSEC1_PHYIDX 0
Timur Tabi89c77842008-02-08 13:15:55 -0600431#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600432
Timur Tabi89c77842008-02-08 13:15:55 -0600433#ifdef CONFIG_TSEC2
434#define CONFIG_HAS_ETH1
435#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600437#define TSEC2_PHY_ADDR 0x1c
438#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
439#define TSEC2_PHYIDX 0
440#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600441
442/* Options are: TSEC[0-1] */
443#define CONFIG_ETHPRIME "TSEC0"
444
Timur Tabi89c77842008-02-08 13:15:55 -0600445#endif
446
Kim Phillips5e918a92008-01-16 00:38:05 -0600447/*
Kim Phillips730e7922008-03-28 14:31:23 -0500448 * SATA
449 */
450#define CONFIG_LIBATA
451#define CONFIG_FSL_SATA
452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500454#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500456#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
457#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500458#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500460#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
461#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500462
463#ifdef CONFIG_FSL_SATA
464#define CONFIG_LBA48
465#define CONFIG_CMD_SATA
466#define CONFIG_DOS_PARTITION
467#define CONFIG_CMD_EXT2
468#endif
469
470/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600471 * Environment
472 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200474 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger5afe9722011-10-11 23:57:19 -0500475 #define CONFIG_ENV_ADDR \
476 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200477 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
478 #define CONFIG_ENV_SIZE 0x4000
Kim Phillips5e918a92008-01-16 00:38:05 -0600479#else
Joe Hershberger5afe9722011-10-11 23:57:19 -0500480 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200481 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200483 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips5e918a92008-01-16 00:38:05 -0600484#endif
485
486#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips5e918a92008-01-16 00:38:05 -0600488
489/*
490 * BOOTP options
491 */
492#define CONFIG_BOOTP_BOOTFILESIZE
493#define CONFIG_BOOTP_BOOTPATH
494#define CONFIG_BOOTP_GATEWAY
495#define CONFIG_BOOTP_HOSTNAME
496
497
498/*
499 * Command line configuration.
500 */
501#include <config_cmd_default.h>
502
503#define CONFIG_CMD_PING
504#define CONFIG_CMD_I2C
505#define CONFIG_CMD_MII
506#define CONFIG_CMD_DATE
507
508#if defined(CONFIG_PCI)
509#define CONFIG_CMD_PCI
510#endif
511
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500513#undef CONFIG_CMD_SAVEENV
Kim Phillips5e918a92008-01-16 00:38:05 -0600514#undef CONFIG_CMD_LOADS
515#endif
516
517#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500518#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips5e918a92008-01-16 00:38:05 -0600519
520#undef CONFIG_WATCHDOG /* watchdog disabled */
521
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400522#define CONFIG_MMC 1
523
524#ifdef CONFIG_MMC
525#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800526#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400527#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
528#define CONFIG_CMD_MMC
529#define CONFIG_GENERIC_MMC
530#define CONFIG_CMD_EXT2
531#define CONFIG_CMD_FAT
532#define CONFIG_DOS_PARTITION
533#endif
534
Kim Phillips5e918a92008-01-16 00:38:05 -0600535/*
536 * Miscellaneous configurable options
537 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500538#define CONFIG_SYS_LONGHELP /* undef to save memory */
539#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips5e918a92008-01-16 00:38:05 -0600540
541#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600543#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600545#endif
546
Joe Hershberger5afe9722011-10-11 23:57:19 -0500547 /* Print Buffer Size */
548#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
549#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
550 /* Boot Argument Buffer Size */
551#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Kim Phillips5e918a92008-01-16 00:38:05 -0600552
553/*
554 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700555 * have to be in the first 256 MB of memory, since this is
Kim Phillips5e918a92008-01-16 00:38:05 -0600556 * the maximum mapped by the Linux kernel during initialization.
557 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500558#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kim Phillips5e918a92008-01-16 00:38:05 -0600559
560/*
561 * Core HID Setup
562 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500563#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500564#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
565 | HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200566#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips5e918a92008-01-16 00:38:05 -0600567
568/*
569 * MMU Setup
570 */
571
Becky Bruce31d82672008-05-08 19:02:12 -0500572#define CONFIG_HIGH_BATS 1 /* High BATs supported */
573
Kim Phillips5e918a92008-01-16 00:38:05 -0600574/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200575#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
576#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Kim Phillips5e918a92008-01-16 00:38:05 -0600577
Joe Hershberger5afe9722011-10-11 23:57:19 -0500578#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500579 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500580 | BATL_MEMCOHERENCE)
581#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
582 | BATU_BL_256M \
583 | BATU_VS \
584 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200585#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
586#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips5e918a92008-01-16 00:38:05 -0600587
Joe Hershberger5afe9722011-10-11 23:57:19 -0500588#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500589 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500590 | BATL_MEMCOHERENCE)
591#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
592 | BATU_BL_256M \
593 | BATU_VS \
594 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
596#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips5e918a92008-01-16 00:38:05 -0600597
598/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500599#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500600 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500601 | BATL_CACHEINHIBIT \
602 | BATL_GUARDEDSTORAGE)
603#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
604 | BATU_BL_8M \
605 | BATU_VS \
606 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
608#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips5e918a92008-01-16 00:38:05 -0600609
610/* L2 Switch: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500611#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500612 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500613 | BATL_CACHEINHIBIT \
614 | BATL_GUARDEDSTORAGE)
615#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
616 | BATU_BL_128K \
617 | BATU_VS \
618 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
620#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips5e918a92008-01-16 00:38:05 -0600621
622/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500623#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500624 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500625 | BATL_MEMCOHERENCE)
626#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
627 | BATU_BL_32M \
628 | BATU_VS \
629 | BATU_VP)
630#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500631 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500632 | BATL_CACHEINHIBIT \
633 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200634#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips5e918a92008-01-16 00:38:05 -0600635
636/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500637#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500638#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
639 | BATU_BL_128K \
640 | BATU_VS \
641 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200642#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
643#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips5e918a92008-01-16 00:38:05 -0600644
645#ifdef CONFIG_PCI
646/* PCI MEM space: cacheable */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500647#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500648 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500649 | BATL_MEMCOHERENCE)
650#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
651 | BATU_BL_256M \
652 | BATU_VS \
653 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200654#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
655#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips5e918a92008-01-16 00:38:05 -0600656/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500657#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500658 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500659 | BATL_CACHEINHIBIT \
660 | BATL_GUARDEDSTORAGE)
661#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
662 | BATU_BL_256M \
663 | BATU_VS \
664 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200665#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
666#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600667#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200668#define CONFIG_SYS_IBAT6L (0)
669#define CONFIG_SYS_IBAT6U (0)
670#define CONFIG_SYS_IBAT7L (0)
671#define CONFIG_SYS_IBAT7U (0)
672#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
673#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
674#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
675#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600676#endif
677
Kim Phillips5e918a92008-01-16 00:38:05 -0600678#if defined(CONFIG_CMD_KGDB)
679#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Kim Phillips5e918a92008-01-16 00:38:05 -0600680#endif
681
682/*
683 * Environment Configuration
684 */
685#define CONFIG_ENV_OVERWRITE
686
Anton Vorontsov18e69a32008-03-14 23:20:18 +0300687#define CONFIG_HAS_FSL_DR_USB
Nikhil Badola6c3c5752014-10-20 16:31:01 +0530688#define CONFIG_CMD_USB
689#define CONFIG_USB_STORAGE
690#define CONFIG_USB_EHCI
691#define CONFIG_USB_EHCI_FSL
692#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov18e69a32008-03-14 23:20:18 +0300693
Joe Hershberger5afe9722011-10-11 23:57:19 -0500694#define CONFIG_NETDEV "eth1"
Kim Phillips5e918a92008-01-16 00:38:05 -0600695
696#define CONFIG_HOSTNAME mpc837x_rdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000697#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershberger5afe9722011-10-11 23:57:19 -0500698#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000699#define CONFIG_BOOTFILE "uImage"
Joe Hershberger5afe9722011-10-11 23:57:19 -0500700 /* U-Boot image on TFTP server */
701#define CONFIG_UBOOTPATH "u-boot.bin"
702#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
Kim Phillips5e918a92008-01-16 00:38:05 -0600703
Joe Hershberger5afe9722011-10-11 23:57:19 -0500704 /* default location for tftp and bootm */
705#define CONFIG_LOADADDR 800000
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500706#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Kim Phillips5e918a92008-01-16 00:38:05 -0600707#define CONFIG_BAUDRATE 115200
708
Kim Phillips5e918a92008-01-16 00:38:05 -0600709#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500710 "netdev=" CONFIG_NETDEV "\0" \
711 "uboot=" CONFIG_UBOOTPATH "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600712 "tftpflash=tftp $loadaddr $uboot;" \
Marek Vasut5368c552012-09-23 17:41:24 +0200713 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
714 " +$filesize; " \
715 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
716 " +$filesize; " \
717 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
718 " $filesize; " \
719 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
720 " +$filesize; " \
721 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
722 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500723 "fdtaddr=780000\0" \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500724 "fdtfile=" CONFIG_FDTFILE "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600725 "ramdiskaddr=1000000\0" \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500726 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600727 "console=ttyS0\0" \
728 "setbootargs=setenv bootargs " \
729 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
730 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500731 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
732 "$netdev:off " \
Kim Phillips5e918a92008-01-16 00:38:05 -0600733 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
734
735#define CONFIG_NFSBOOTCOMMAND \
736 "setenv rootdev /dev/nfs;" \
737 "run setbootargs;" \
738 "run setipargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
742
743#define CONFIG_RAMBOOTCOMMAND \
744 "setenv rootdev /dev/ram;" \
745 "run setbootargs;" \
746 "tftp $ramdiskaddr $ramdiskfile;" \
747 "tftp $loadaddr $bootfile;" \
748 "tftp $fdtaddr $fdtfile;" \
749 "bootm $loadaddr $ramdiskaddr $fdtaddr"
750
Kim Phillips5e918a92008-01-16 00:38:05 -0600751#endif /* __CONFIG_H */