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Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05301/*
York Sunc60dee02014-03-27 17:54:48 -07002 * Copyright 2013-2014 Freescale Semiconductor, Inc.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05303 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * T1040 QDS board configuration file
28 */
29#define CONFIG_T1040QDS
30#define CONFIG_PHYS_64BIT
vijay rai2aea6612014-11-18 12:21:13 +053031#define CONFIG_SYS_GENERIC_BOARD
32#define CONFIG_DISPLAY_BOARDINFO
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053033
34#ifdef CONFIG_RAMBOOT_PBL
35#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
36#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090037#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
38#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053039#endif
40
41/* High Level Configuration Options */
42#define CONFIG_BOOKE
43#define CONFIG_E500 /* BOOKE e500 family */
44#define CONFIG_E500MC /* BOOKE e500mc family */
45#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053046#define CONFIG_MP /* support multiple processors */
47
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080048/* support deep sleep */
49#define CONFIG_DEEP_SLEEP
50#define CONFIG_SILENT_CONSOLE
51
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053052#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053053#define CONFIG_SYS_TEXT_BASE 0xeff40000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053054#endif
55
56#ifndef CONFIG_RESET_VECTOR_ADDRESS
57#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
58#endif
59
60#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
61#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
62#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053063#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053064#define CONFIG_PCI /* Enable PCI/PCIE */
65#define CONFIG_PCI_INDIRECT_BRIDGE
66#define CONFIG_PCIE1 /* PCIE controler 1 */
67#define CONFIG_PCIE2 /* PCIE controler 2 */
68#define CONFIG_PCIE3 /* PCIE controler 3 */
69#define CONFIG_PCIE4 /* PCIE controler 4 */
70
71#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
72#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
73
74#define CONFIG_FSL_LAW /* Use common FSL init code */
75
76#define CONFIG_ENV_OVERWRITE
77
78#ifdef CONFIG_SYS_NO_FLASH
79#define CONFIG_ENV_IS_NOWHERE
80#else
81#define CONFIG_FLASH_CFI_DRIVER
82#define CONFIG_SYS_FLASH_CFI
83#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
84#endif
85
86#ifndef CONFIG_SYS_NO_FLASH
87#if defined(CONFIG_SPIFLASH)
88#define CONFIG_SYS_EXTRA_ENV_RELOC
89#define CONFIG_ENV_IS_IN_SPI_FLASH
90#define CONFIG_ENV_SPI_BUS 0
91#define CONFIG_ENV_SPI_CS 0
92#define CONFIG_ENV_SPI_MAX_HZ 10000000
93#define CONFIG_ENV_SPI_MODE 0
94#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
95#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
96#define CONFIG_ENV_SECT_SIZE 0x10000
97#elif defined(CONFIG_SDCARD)
98#define CONFIG_SYS_EXTRA_ENV_RELOC
99#define CONFIG_ENV_IS_IN_MMC
100#define CONFIG_SYS_MMC_ENV_DEV 0
101#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530102#define CONFIG_ENV_OFFSET (512 * 1658)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530103#elif defined(CONFIG_NAND)
104#define CONFIG_SYS_EXTRA_ENV_RELOC
105#define CONFIG_ENV_IS_IN_NAND
106#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530107#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530108#else
109#define CONFIG_ENV_IS_IN_FLASH
110#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
111#define CONFIG_ENV_SIZE 0x2000
112#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
113#endif
114#else /* CONFIG_SYS_NO_FLASH */
115#define CONFIG_ENV_SIZE 0x2000
116#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
117#endif
118
119#ifndef __ASSEMBLY__
120unsigned long get_board_sys_clk(void);
121unsigned long get_board_ddr_clk(void);
122#endif
123
124#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
125#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
126
127/*
128 * These can be toggled for performance analysis, otherwise use default.
129 */
130#define CONFIG_SYS_CACHE_STASHING
131#define CONFIG_BACKSIDE_L2_CACHE
132#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
133#define CONFIG_BTB /* toggle branch predition */
134#define CONFIG_DDR_ECC
135#ifdef CONFIG_DDR_ECC
136#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
137#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
138#endif
139
140#define CONFIG_ENABLE_36BIT_PHYS
141
142#define CONFIG_ADDR_MAP
143#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
144
145#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
146#define CONFIG_SYS_MEMTEST_END 0x00400000
147#define CONFIG_SYS_ALT_MEMTEST
148#define CONFIG_PANIC_HANG /* do not reset board on panic */
149
150/*
151 * Config the L3 Cache as L3 SRAM
152 */
153#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
154
155#define CONFIG_SYS_DCSRBAR 0xf0000000
156#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
157
158/* EEPROM */
159#define CONFIG_ID_EEPROM
160#define CONFIG_SYS_I2C_EEPROM_NXID
161#define CONFIG_SYS_EEPROM_BUS_NUM 0
162#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
163#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
164#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
165#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
166
167/*
168 * DDR Setup
169 */
170#define CONFIG_VERY_BIG_RAM
171#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
172#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
173
174/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
175#define CONFIG_DIMM_SLOTS_PER_CTLR 1
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530176#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530177
178#define CONFIG_DDR_SPD
York Sunc60dee02014-03-27 17:54:48 -0700179#ifndef CONFIG_SYS_FSL_DDR4
York Sun5614e712013-09-30 09:22:09 -0700180#define CONFIG_SYS_FSL_DDR3
York Sunc60dee02014-03-27 17:54:48 -0700181#endif
York Sun1b2af9b2014-10-27 11:45:11 -0700182#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530183
184#define CONFIG_SYS_SPD_BUS_NUM 0
185#define SPD_EEPROM_ADDRESS 0x51
186
187#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
188
189/*
190 * IFC Definitions
191 */
192#define CONFIG_SYS_FLASH_BASE 0xe0000000
193#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
194
195#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
196#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
197 + 0x8000000) | \
198 CSPR_PORT_SIZE_16 | \
199 CSPR_MSEL_NOR | \
200 CSPR_V)
201#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
202#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
203 CSPR_PORT_SIZE_16 | \
204 CSPR_MSEL_NOR | \
205 CSPR_V)
206#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530207
208/*
209 * TDM Definition
210 */
211#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
212
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530213/* NOR Flash Timing Params */
214#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
215#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
216 FTIM0_NOR_TEADC(0x5) | \
217 FTIM0_NOR_TEAHC(0x5))
218#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
219 FTIM1_NOR_TRAD_NOR(0x1A) |\
220 FTIM1_NOR_TSEQRAD_NOR(0x13))
221#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
222 FTIM2_NOR_TCH(0x4) | \
223 FTIM2_NOR_TWPH(0x0E) | \
224 FTIM2_NOR_TWP(0x1c))
225#define CONFIG_SYS_NOR_FTIM3 0x0
226
227#define CONFIG_SYS_FLASH_QUIET_TEST
228#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
229
230#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
231#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
232#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
233#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
234
235#define CONFIG_SYS_FLASH_EMPTY_INFO
236#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
237 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
238#define CONFIG_FSL_QIXIS /* use common QIXIS code */
239#define QIXIS_BASE 0xffdf0000
240#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
241#define QIXIS_LBMAP_SWITCH 0x06
242#define QIXIS_LBMAP_MASK 0x0f
243#define QIXIS_LBMAP_SHIFT 0
244#define QIXIS_LBMAP_DFLTBANK 0x00
245#define QIXIS_LBMAP_ALTBANK 0x04
246#define QIXIS_RST_CTL_RESET 0x31
247#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
248#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
249#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Prabhakar Kushwaha8c618dd2013-12-26 12:40:55 +0530250#define QIXIS_RST_FORCE_MEM 0x01
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530251
252#define CONFIG_SYS_CSPR3_EXT (0xf)
253#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
254 | CSPR_PORT_SIZE_8 \
255 | CSPR_MSEL_GPCM \
256 | CSPR_V)
257#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
258#define CONFIG_SYS_CSOR3 0x0
259/* QIXIS Timing parameters for IFC CS3 */
260#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
261 FTIM0_GPCM_TEADC(0x0e) | \
262 FTIM0_GPCM_TEAHC(0x0e))
263#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
264 FTIM1_GPCM_TRAD(0x3f))
265#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Prabhakar Kushwaha562de1d2013-12-12 12:09:01 +0530266 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530267 FTIM2_GPCM_TWP(0x1f))
268#define CONFIG_SYS_CS3_FTIM3 0x0
269
270#define CONFIG_NAND_FSL_IFC
271#define CONFIG_SYS_NAND_BASE 0xff800000
272#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
273
274#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
275#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
276 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
277 | CSPR_MSEL_NAND /* MSEL = NAND */ \
278 | CSPR_V)
279#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
280
281#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
282 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
283 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
284 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
285 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
286 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
287 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
288
289#define CONFIG_SYS_NAND_ONFI_DETECTION
290
291/* ONFI NAND Flash mode0 Timing Params */
292#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
293 FTIM0_NAND_TWP(0x18) | \
294 FTIM0_NAND_TWCHT(0x07) | \
295 FTIM0_NAND_TWH(0x0a))
296#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
297 FTIM1_NAND_TWBE(0x39) | \
298 FTIM1_NAND_TRR(0x0e) | \
299 FTIM1_NAND_TRP(0x18))
300#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
301 FTIM2_NAND_TREH(0x0a) | \
302 FTIM2_NAND_TWHRE(0x1e))
303#define CONFIG_SYS_NAND_FTIM3 0x0
304
305#define CONFIG_SYS_NAND_DDR_LAW 11
306#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
307#define CONFIG_SYS_MAX_NAND_DEVICE 1
308#define CONFIG_MTD_NAND_VERIFY_WRITE
309#define CONFIG_CMD_NAND
310
311#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
312
313#if defined(CONFIG_NAND)
314#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
315#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
316#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
317#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
318#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
319#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
320#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
321#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
322#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
323#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
324#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
325#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
326#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
327#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
328#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
329#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
330#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
331#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
332#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
333#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
334#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
335#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
336#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
337#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
338#else
339#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
340#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
341#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
342#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
343#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
344#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
345#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
346#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
347#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
348#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
349#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
350#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
351#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
352#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
353#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
354#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
355#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
356#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
357#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
358#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
359#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
360#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
361#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
362#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
363#endif
364
365#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
366
367#if defined(CONFIG_RAMBOOT_PBL)
368#define CONFIG_SYS_RAMBOOT
369#endif
370
371#define CONFIG_BOARD_EARLY_INIT_R
372#define CONFIG_MISC_INIT_R
373
374#define CONFIG_HWCONFIG
375
376/* define to use L1 as initial stack */
377#define CONFIG_L1_INIT_RAM
378#define CONFIG_SYS_INIT_RAM_LOCK
379#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
380#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
381#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
382/* The assembler doesn't like typecast */
383#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
384 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
385 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
386#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
387
388#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
389 GENERATED_GBL_DATA_SIZE)
390#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
391
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530392#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Priyanka Jain337b0c52014-02-26 16:11:53 +0530393#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530394
395/* Serial Port - controlled on board with jumper J8
396 * open - index 2
397 * shorted - index 1
398 */
399#define CONFIG_CONS_INDEX 1
400#define CONFIG_SYS_NS16550
401#define CONFIG_SYS_NS16550_SERIAL
402#define CONFIG_SYS_NS16550_REG_SIZE 1
403#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
404
405#define CONFIG_SYS_BAUDRATE_TABLE \
406 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
407
408#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
409#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
410#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
411#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
412#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
413#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
414
415/* Use the HUSH parser */
416#define CONFIG_SYS_HUSH_PARSER
417#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
418
Priyanka Jain337b0c52014-02-26 16:11:53 +0530419/* Video */
420#define CONFIG_FSL_DIU_FB
421#ifdef CONFIG_FSL_DIU_FB
Wang Dongshengc53711b2014-03-19 10:47:55 +0800422#define CONFIG_FSL_DIU_CH7301
Priyanka Jain337b0c52014-02-26 16:11:53 +0530423#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
424#define CONFIG_VIDEO
425#define CONFIG_CMD_BMP
426#define CONFIG_CFB_CONSOLE
427#define CONFIG_VIDEO_SW_CURSOR
428#define CONFIG_VGA_AS_SINGLE_DEVICE
429#define CONFIG_VIDEO_LOGO
430#define CONFIG_VIDEO_BMP_LOGO
431#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
432/*
433 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
434 * disable empty flash sector detection, which is I/O-intensive.
435 */
436#undef CONFIG_SYS_FLASH_EMPTY_INFO
437#endif
438
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530439/* pass open firmware flat tree */
440#define CONFIG_OF_LIBFDT
441#define CONFIG_OF_BOARD_SETUP
442#define CONFIG_OF_STDOUT_VIA_ALIAS
443
444/* new uImage format support */
445#define CONFIG_FIT
446#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
447
448/* I2C */
449#define CONFIG_SYS_I2C
450#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530451#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800452#define CONFIG_SYS_FSL_I2C2_SPEED 50000
453#define CONFIG_SYS_FSL_I2C3_SPEED 50000
454#define CONFIG_SYS_FSL_I2C4_SPEED 50000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530455#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530456#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800457#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
458#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530459#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800460#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
461#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
462#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530463
464#define I2C_MUX_PCA_ADDR 0x77
465#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
466
467
468/* I2C bus multiplexer */
469#define I2C_MUX_CH_DEFAULT 0x8
Priyanka Jain337b0c52014-02-26 16:11:53 +0530470#define I2C_MUX_CH_DIU 0xC
471
472/* LDI/DVI Encoder for display */
473#define CONFIG_SYS_I2C_LDI_ADDR 0x38
474#define CONFIG_SYS_I2C_DVI_ADDR 0x75
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530475
476/*
477 * RTC configuration
478 */
479#define RTC
480#define CONFIG_RTC_DS3231 1
481#define CONFIG_SYS_I2C_RTC_ADDR 0x68
482
483/*
484 * eSPI - Enhanced SPI
485 */
486#define CONFIG_FSL_ESPI
487#define CONFIG_SPI_FLASH
488#define CONFIG_SPI_FLASH_STMICRO
489#define CONFIG_SPI_FLASH_SST
490#define CONFIG_SPI_FLASH_EON
491#define CONFIG_CMD_SF
492#define CONFIG_SF_DEFAULT_SPEED 10000000
493#define CONFIG_SF_DEFAULT_MODE 0
494
495/*
496 * General PCI
497 * Memory space is mapped 1-1, but I/O space must start from 0.
498 */
499
500#ifdef CONFIG_PCI
501/* controller 1, direct to uli, tgtid 3, Base address 20000 */
502#ifdef CONFIG_PCIE1
503#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
504#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
505#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
506#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
507#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
508#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
509#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
510#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
511#endif
512
513/* controller 2, Slot 2, tgtid 2, Base address 201000 */
514#ifdef CONFIG_PCIE2
515#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
516#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
517#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
518#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
519#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
520#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
521#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
522#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
523#endif
524
525/* controller 3, Slot 1, tgtid 1, Base address 202000 */
526#ifdef CONFIG_PCIE3
527#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
528#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
529#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
530#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
531#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
532#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
533#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
534#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
535#endif
536
537/* controller 4, Base address 203000 */
538#ifdef CONFIG_PCIE4
539#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
540#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
541#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
542#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
543#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
544#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
545#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
546#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
547#endif
548
549#define CONFIG_PCI_PNP /* do pci plug-and-play */
550#define CONFIG_E1000
551
552#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
553#define CONFIG_DOS_PARTITION
554#endif /* CONFIG_PCI */
555
556/* SATA */
557#define CONFIG_FSL_SATA_V2
558#ifdef CONFIG_FSL_SATA_V2
559#define CONFIG_LIBATA
560#define CONFIG_FSL_SATA
561
562#define CONFIG_SYS_SATA_MAX_DEVICE 2
563#define CONFIG_SATA1
564#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
565#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
566#define CONFIG_SATA2
567#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
568#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
569
570#define CONFIG_LBA48
571#define CONFIG_CMD_SATA
572#define CONFIG_DOS_PARTITION
573#define CONFIG_CMD_EXT2
574#endif
575
576/*
577* USB
578*/
579#define CONFIG_HAS_FSL_DR_USB
580
581#ifdef CONFIG_HAS_FSL_DR_USB
582#define CONFIG_USB_EHCI
583
584#ifdef CONFIG_USB_EHCI
585#define CONFIG_CMD_USB
586#define CONFIG_USB_STORAGE
587#define CONFIG_USB_EHCI_FSL
588#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
589#define CONFIG_CMD_EXT2
590#endif
591#endif
592
593#define CONFIG_MMC
594
595#ifdef CONFIG_MMC
596#define CONFIG_FSL_ESDHC
597#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
598#define CONFIG_CMD_MMC
599#define CONFIG_GENERIC_MMC
600#define CONFIG_CMD_EXT2
601#define CONFIG_CMD_FAT
602#define CONFIG_DOS_PARTITION
603#endif
604
605/* Qman/Bman */
606#ifndef CONFIG_NOBQFMAN
607#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500608#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530609#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
610#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
611#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500612#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
613#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
614#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
615#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
616#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
617 CONFIG_SYS_BMAN_CENA_SIZE)
618#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
619#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500620#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530621#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
622#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
623#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500624#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
625#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
626#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
627#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
628#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
629 CONFIG_SYS_QMAN_CENA_SIZE)
630#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
631#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530632
633#define CONFIG_SYS_DPAA_FMAN
634#define CONFIG_SYS_DPAA_PME
635
Zhao Qiang6259e292014-03-21 16:21:46 +0800636#define CONFIG_QE
637#define CONFIG_U_QE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530638/* Default address of microcode for the Linux Fman driver */
639#if defined(CONFIG_SPIFLASH)
640/*
641 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
642 * env, so we got 0x110000.
643 */
644#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800645#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530646#elif defined(CONFIG_SDCARD)
647/*
648 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530649 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
650 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530651 */
652#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800653#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530654#elif defined(CONFIG_NAND)
655#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800656#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530657#else
658#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800659#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Zhao Qiang6259e292014-03-21 16:21:46 +0800660#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530661#endif
662#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
663#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
664#endif /* CONFIG_NOBQFMAN */
665
666#ifdef CONFIG_SYS_DPAA_FMAN
667#define CONFIG_FMAN_ENET
668#define CONFIG_PHYLIB_10G
669#define CONFIG_PHY_VITESSE
670#define CONFIG_PHY_REALTEK
671#define CONFIG_PHY_TERANETICS
672#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
673#define SGMII_CARD_PORT2_PHY_ADDR 0x10
674#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
675#define SGMII_CARD_PORT4_PHY_ADDR 0x11
676#endif
677
678#ifdef CONFIG_FMAN_ENET
Prabhakar Kushwaha5b7672f2014-01-27 15:55:20 +0530679#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
680#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530681
682#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
683#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
684#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
685#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
686
687#define CONFIG_MII /* MII PHY management */
688#define CONFIG_ETHPRIME "FM1@DTSEC1"
689#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
690#endif
691
692/*
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530693 * Dynamic MTD Partition support with mtdparts
694 */
695#ifndef CONFIG_SYS_NO_FLASH
696#define CONFIG_MTD_DEVICE
697#define CONFIG_MTD_PARTITIONS
698#define CONFIG_CMD_MTDPARTS
699#define CONFIG_FLASH_CFI_MTD
700#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
701 "spi0=spife110000.0"
702#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
703 "128k(dtb),96m(fs),-(user);"\
704 "fff800000.flash:2m(uboot),9m(kernel),"\
705 "128k(dtb),96m(fs),-(user);spife110000.0:" \
706 "2m(uboot),9m(kernel),128k(dtb),-(user)"
707#endif
708
709/*
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530710 * Environment
711 */
712#define CONFIG_LOADS_ECHO /* echo on for serial download */
713#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
714
715/*
716 * Command line configuration.
717 */
718#include <config_cmd_default.h>
719
720#define CONFIG_CMD_DATE
721#define CONFIG_CMD_DHCP
722#define CONFIG_CMD_EEPROM
723#define CONFIG_CMD_ELF
724#define CONFIG_CMD_ERRATA
725#define CONFIG_CMD_GREPENV
726#define CONFIG_CMD_IRQ
727#define CONFIG_CMD_I2C
728#define CONFIG_CMD_MII
729#define CONFIG_CMD_PING
730#define CONFIG_CMD_REGINFO
731#define CONFIG_CMD_SETEXPR
732
733#ifdef CONFIG_PCI
734#define CONFIG_CMD_PCI
735#define CONFIG_CMD_NET
736#endif
737
Ruchika Gupta737537e2014-10-15 11:35:31 +0530738/* Hash command with SHA acceleration supported in hardware */
739#ifdef CONFIG_FSL_CAAM
740#define CONFIG_CMD_HASH
741#define CONFIG_SHA_HW_ACCEL
742#endif
743
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530744/*
745 * Miscellaneous configurable options
746 */
747#define CONFIG_SYS_LONGHELP /* undef to save memory */
748#define CONFIG_CMDLINE_EDITING /* Command-line editing */
749#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
750#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530751#ifdef CONFIG_CMD_KGDB
752#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
753#else
754#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
755#endif
756#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
757#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
758#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530759
760/*
761 * For booting Linux, the board info and command line data
762 * have to be in the first 64 MB of memory, since this is
763 * the maximum mapped by the Linux kernel during initialization.
764 */
765#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
766#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
767
768#ifdef CONFIG_CMD_KGDB
769#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530770#endif
771
772/*
773 * Environment Configuration
774 */
775#define CONFIG_ROOTPATH "/opt/nfsroot"
776#define CONFIG_BOOTFILE "uImage"
777#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
778
779/* default location for tftp and bootm */
780#define CONFIG_LOADADDR 1000000
781
782#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
783
784#define CONFIG_BAUDRATE 115200
785
786#define __USB_PHY_TYPE utmi
787
788#define CONFIG_EXTRA_ENV_SETTINGS \
York Sun1b2af9b2014-10-27 11:45:11 -0700789 "hwconfig=fsl_ddr:bank_intlv=auto;" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530790 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
791 "netdev=eth0\0" \
Priyanka Jain337b0c52014-02-26 16:11:53 +0530792 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530793 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
794 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
795 "tftpflash=tftpboot $loadaddr $uboot && " \
796 "protect off $ubootaddr +$filesize && " \
797 "erase $ubootaddr +$filesize && " \
798 "cp.b $loadaddr $ubootaddr $filesize && " \
799 "protect on $ubootaddr +$filesize && " \
800 "cmp.b $loadaddr $ubootaddr $filesize\0" \
801 "consoledev=ttyS0\0" \
802 "ramdiskaddr=2000000\0" \
803 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
804 "fdtaddr=c00000\0" \
805 "fdtfile=t1040qds/t1040qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500806 "bdev=sda3\0"
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530807
808#define CONFIG_LINUX \
809 "setenv bootargs root=/dev/ram rw " \
810 "console=$consoledev,$baudrate $othbootargs;" \
811 "setenv ramdiskaddr 0x02000000;" \
812 "setenv fdtaddr 0x00c00000;" \
813 "setenv loadaddr 0x1000000;" \
814 "bootm $loadaddr $ramdiskaddr $fdtaddr"
815
816#define CONFIG_HDBOOT \
817 "setenv bootargs root=/dev/$bdev rw " \
818 "console=$consoledev,$baudrate $othbootargs;" \
819 "tftp $loadaddr $bootfile;" \
820 "tftp $fdtaddr $fdtfile;" \
821 "bootm $loadaddr - $fdtaddr"
822
823#define CONFIG_NFSBOOTCOMMAND \
824 "setenv bootargs root=/dev/nfs rw " \
825 "nfsroot=$serverip:$rootpath " \
826 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
827 "console=$consoledev,$baudrate $othbootargs;" \
828 "tftp $loadaddr $bootfile;" \
829 "tftp $fdtaddr $fdtfile;" \
830 "bootm $loadaddr - $fdtaddr"
831
832#define CONFIG_RAMBOOTCOMMAND \
833 "setenv bootargs root=/dev/ram rw " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "tftp $ramdiskaddr $ramdiskfile;" \
836 "tftp $loadaddr $bootfile;" \
837 "tftp $fdtaddr $fdtfile;" \
838 "bootm $loadaddr $ramdiskaddr $fdtaddr"
839
840#define CONFIG_BOOTCOMMAND CONFIG_LINUX
841
842#ifdef CONFIG_SECURE_BOOT
843#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530844#define CONFIG_CMD_BLOB
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530845#endif
846
847#endif /* __CONFIG_H */