blob: 59b14e90610b9d395155ec9dbf43c0c07e4aa5d4 [file] [log] [blame]
Vladimir Barinov60c04672015-02-14 01:06:13 +03001/*
2 * include/configs/porter.h
3 * This file is Porter board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __PORTER_H
12#define __PORTER_H
13
14#undef DEBUG
15#define CONFIG_R8A7791
16#define CONFIG_RMOBILE_BOARD_STRING "Porter"
17
18#include "rcar-gen2-common.h"
19
20#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
21#define CONFIG_SYS_TEXT_BASE 0x70000000
22#else
23#define CONFIG_SYS_TEXT_BASE 0xE6304000
24#endif
25
26#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
27#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
28#else
29#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
30#endif
31#define STACK_AREA_SIZE 0xC000
32#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
36#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
39
40/* SCIF */
41#define CONFIG_SCIF_CONSOLE
42
43/* FLASH */
44#define CONFIG_SPI
Vladimir Barinov60c04672015-02-14 01:06:13 +030045#define CONFIG_SH_QSPI
Vladimir Barinov60c04672015-02-14 01:06:13 +030046#define CONFIG_SPI_FLASH_SPANSION
47#define CONFIG_SPI_FLASH_QUAD
48#define CONFIG_SYS_NO_FLASH
49
50/* SH Ether */
Vladimir Barinov60c04672015-02-14 01:06:13 +030051#define CONFIG_SH_ETHER
52#define CONFIG_SH_ETHER_USE_PORT 0
53#define CONFIG_SH_ETHER_PHY_ADDR 0x1
54#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
55#define CONFIG_SH_ETHER_CACHE_WRITEBACK
56#define CONFIG_SH_ETHER_CACHE_INVALIDATE
57#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
58#define CONFIG_PHYLIB
59#define CONFIG_PHY_MICREL
60#define CONFIG_BITBANGMII
61#define CONFIG_BITBANGMII_MULTI
62
63/* Board Clock */
64#define RMOBILE_XTAL_CLK 20000000u
65#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
66#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
67#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
68#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
69
70#define CONFIG_SYS_TMU_CLK_DIV 4
71
72/* i2c */
73#define CONFIG_CMD_I2C
74#define CONFIG_SYS_I2C
75#define CONFIG_SYS_I2C_SH
76#define CONFIG_SYS_I2C_SLAVE 0x7F
77#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
78#define CONFIG_SYS_I2C_SH_SPEED0 400000
79#define CONFIG_SYS_I2C_SH_SPEED1 400000
80#define CONFIG_SYS_I2C_SH_SPEED2 400000
81#define CONFIG_SH_I2C_DATA_HIGH 4
82#define CONFIG_SH_I2C_DATA_LOW 5
83#define CONFIG_SH_I2C_CLOCK 10000000
84
85#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
86
87/* USB */
88#define CONFIG_USB_EHCI
89#define CONFIG_USB_EHCI_RMOBILE
90#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
91#define CONFIG_USB_STORAGE
92
93/* SD */
94#define CONFIG_MMC
95#define CONFIG_CMD_MMC
96#define CONFIG_GENERIC_MMC
97#define CONFIG_SH_SDHI_FREQ 97500000
98
99/* Module stop status bits */
100/* INTC-RT */
101#define CONFIG_SMSTP0_ENA 0x00400000
102/* MSIF */
103#define CONFIG_SMSTP2_ENA 0x00002000
104/* INTC-SYS, IRQC */
105#define CONFIG_SMSTP4_ENA 0x00000180
106/* SCIF0 */
107#define CONFIG_SMSTP7_ENA 0x00200000
108
109#endif /* __PORTER_H */