blob: 23ee1e6cfa2c90b430c9e2cea2c883349245808e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkdd7d41f2002-09-18 20:04:01 +00002/*
3 * (C) Copyright 2001
4 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
wdenkdd7d41f2002-09-18 20:04:01 +00005 */
6
7/*
8 * MII Utilities
9 */
10
11#include <common.h>
12#include <command.h>
wdenke35745b2004-04-18 23:32:11 +000013#include <miiphy.h>
14
wdenk24711112004-04-18 22:57:51 +000015typedef struct _MII_field_desc_t {
16 ushort hi;
17 ushort lo;
18 ushort mask;
Trent Piepho4ef32312019-05-09 19:23:39 +000019 const char *name;
wdenk24711112004-04-18 22:57:51 +000020} MII_field_desc_t;
21
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040022static const MII_field_desc_t reg_0_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000023 { 15, 15, 0x01, "reset" },
24 { 14, 14, 0x01, "loopback" },
25 { 13, 6, 0x81, "speed selection" }, /* special */
26 { 12, 12, 0x01, "A/N enable" },
27 { 11, 11, 0x01, "power-down" },
28 { 10, 10, 0x01, "isolate" },
29 { 9, 9, 0x01, "restart A/N" },
30 { 8, 8, 0x01, "duplex" }, /* special */
31 { 7, 7, 0x01, "collision test enable" },
32 { 5, 0, 0x3f, "(reserved)" }
33};
34
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040035static const MII_field_desc_t reg_1_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000036 { 15, 15, 0x01, "100BASE-T4 able" },
37 { 14, 14, 0x01, "100BASE-X full duplex able" },
38 { 13, 13, 0x01, "100BASE-X half duplex able" },
39 { 12, 12, 0x01, "10 Mbps full duplex able" },
40 { 11, 11, 0x01, "10 Mbps half duplex able" },
41 { 10, 10, 0x01, "100BASE-T2 full duplex able" },
42 { 9, 9, 0x01, "100BASE-T2 half duplex able" },
43 { 8, 8, 0x01, "extended status" },
44 { 7, 7, 0x01, "(reserved)" },
45 { 6, 6, 0x01, "MF preamble suppression" },
46 { 5, 5, 0x01, "A/N complete" },
47 { 4, 4, 0x01, "remote fault" },
48 { 3, 3, 0x01, "A/N able" },
49 { 2, 2, 0x01, "link status" },
50 { 1, 1, 0x01, "jabber detect" },
51 { 0, 0, 0x01, "extended capabilities" },
52};
53
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040054static const MII_field_desc_t reg_2_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000055 { 15, 0, 0xffff, "OUI portion" },
56};
57
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040058static const MII_field_desc_t reg_3_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000059 { 15, 10, 0x3f, "OUI portion" },
60 { 9, 4, 0x3f, "manufacturer part number" },
61 { 3, 0, 0x0f, "manufacturer rev. number" },
62};
63
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040064static const MII_field_desc_t reg_4_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000065 { 15, 15, 0x01, "next page able" },
Stephan Bauroth57d33d42013-08-08 13:44:41 +020066 { 14, 14, 0x01, "(reserved)" },
wdenk24711112004-04-18 22:57:51 +000067 { 13, 13, 0x01, "remote fault" },
Stephan Bauroth57d33d42013-08-08 13:44:41 +020068 { 12, 12, 0x01, "(reserved)" },
wdenk24711112004-04-18 22:57:51 +000069 { 11, 11, 0x01, "asymmetric pause" },
70 { 10, 10, 0x01, "pause enable" },
71 { 9, 9, 0x01, "100BASE-T4 able" },
72 { 8, 8, 0x01, "100BASE-TX full duplex able" },
73 { 7, 7, 0x01, "100BASE-TX able" },
74 { 6, 6, 0x01, "10BASE-T full duplex able" },
75 { 5, 5, 0x01, "10BASE-T able" },
Trent Piepho4ef32312019-05-09 19:23:39 +000076 { 4, 0, 0x1f, "selector" },
wdenk24711112004-04-18 22:57:51 +000077};
78
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -040079static const MII_field_desc_t reg_5_desc_tbl[] = {
wdenk24711112004-04-18 22:57:51 +000080 { 15, 15, 0x01, "next page able" },
81 { 14, 14, 0x01, "acknowledge" },
82 { 13, 13, 0x01, "remote fault" },
83 { 12, 12, 0x01, "(reserved)" },
84 { 11, 11, 0x01, "asymmetric pause able" },
85 { 10, 10, 0x01, "pause able" },
86 { 9, 9, 0x01, "100BASE-T4 able" },
87 { 8, 8, 0x01, "100BASE-X full duplex able" },
88 { 7, 7, 0x01, "100BASE-TX able" },
89 { 6, 6, 0x01, "10BASE-T full duplex able" },
90 { 5, 5, 0x01, "10BASE-T able" },
Trent Piepho4ef32312019-05-09 19:23:39 +000091 { 4, 0, 0x1f, "partner selector" },
wdenk24711112004-04-18 22:57:51 +000092};
Trent Piepho4ef32312019-05-09 19:23:39 +000093
Trent Piepho95637862019-05-09 19:23:47 +000094static const MII_field_desc_t reg_9_desc_tbl[] = {
95 { 15, 13, 0x07, "test mode" },
96 { 12, 12, 0x01, "manual master/slave enable" },
97 { 11, 11, 0x01, "manual master/slave value" },
98 { 10, 10, 0x01, "multi/single port" },
99 { 9, 9, 0x01, "1000BASE-T full duplex able" },
100 { 8, 8, 0x01, "1000BASE-T half duplex able" },
101 { 7, 7, 0x01, "automatic TDR on link down" },
102 { 6, 6, 0x7f, "(reserved)" },
103};
104
105static const MII_field_desc_t reg_10_desc_tbl[] = {
106 { 15, 15, 0x01, "master/slave config fault" },
107 { 14, 14, 0x01, "master/slave config result" },
108 { 13, 13, 0x01, "local receiver status OK" },
109 { 12, 12, 0x01, "remote receiver status OK" },
110 { 11, 11, 0x01, "1000BASE-T full duplex able" },
111 { 10, 10, 0x01, "1000BASE-T half duplex able" },
112 { 9, 8, 0x03, "(reserved)" },
113 { 7, 0, 0xff, "1000BASE-T idle error counter"},
114};
115
Trent Piepho4ef32312019-05-09 19:23:39 +0000116typedef struct _MII_reg_desc_t {
117 ushort regno;
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -0400118 const MII_field_desc_t *pdesc;
wdenk24711112004-04-18 22:57:51 +0000119 ushort len;
Trent Piepho4ef32312019-05-09 19:23:39 +0000120 const char *name;
121} MII_reg_desc_t;
wdenk24711112004-04-18 22:57:51 +0000122
Trent Piepho4ef32312019-05-09 19:23:39 +0000123static const MII_reg_desc_t mii_reg_desc_tbl[] = {
124 { MII_BMCR, reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
125 "PHY control register" },
126 { MII_BMSR, reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl),
127 "PHY status register" },
128 { MII_PHYSID1, reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl),
129 "PHY ID 1 register" },
130 { MII_PHYSID2, reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl),
131 "PHY ID 2 register" },
132 { MII_ADVERTISE, reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl),
133 "Autonegotiation advertisement register" },
134 { MII_LPA, reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl),
135 "Autonegotiation partner abilities register" },
Trent Piepho95637862019-05-09 19:23:47 +0000136 { MII_CTRL1000, reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
137 "1000BASE-T control register" },
138 { MII_STAT1000, reg_10_desc_tbl, ARRAY_SIZE(reg_10_desc_tbl),
139 "1000BASE-T status register" },
wdenk24711112004-04-18 22:57:51 +0000140};
141
142static void dump_reg(
143 ushort regval,
Trent Piepho4ef32312019-05-09 19:23:39 +0000144 const MII_reg_desc_t *prd);
wdenk24711112004-04-18 22:57:51 +0000145
Trent Piepho4ef32312019-05-09 19:23:39 +0000146static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
147 ushort regval);
wdenk24711112004-04-18 22:57:51 +0000148
Trent Piepho4ef32312019-05-09 19:23:39 +0000149static void MII_dump(const ushort *regvals, uchar reglo, uchar reghi)
wdenk24711112004-04-18 22:57:51 +0000150{
151 ulong i;
152
Trent Piepho4ef32312019-05-09 19:23:39 +0000153 for (i = 0; i < ARRAY_SIZE(mii_reg_desc_tbl); i++) {
154 const uchar reg = mii_reg_desc_tbl[i].regno;
155
156 if (reg >= reglo && reg <= reghi)
157 dump_reg(regvals[reg - reglo], &mii_reg_desc_tbl[i]);
wdenk24711112004-04-18 22:57:51 +0000158 }
159}
160
Trent Piepho4ef32312019-05-09 19:23:39 +0000161/* Print out field position, value, name */
162static void dump_field(const MII_field_desc_t *pdesc, ushort regval)
163{
164 if (pdesc->hi == pdesc->lo)
165 printf("%2u ", pdesc->lo);
166 else
167 printf("%2u-%2u", pdesc->hi, pdesc->lo);
168
169 printf(" = %5u %s", (regval >> pdesc->lo) & pdesc->mask,
170 pdesc->name);
171}
172
wdenk24711112004-04-18 22:57:51 +0000173static void dump_reg(
174 ushort regval,
Trent Piepho4ef32312019-05-09 19:23:39 +0000175 const MII_reg_desc_t *prd)
wdenk24711112004-04-18 22:57:51 +0000176{
177 ulong i;
178 ushort mask_in_place;
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -0400179 const MII_field_desc_t *pdesc;
wdenk24711112004-04-18 22:57:51 +0000180
181 printf("%u. (%04hx) -- %s --\n",
182 prd->regno, regval, prd->name);
183
Trent Piepho4ef32312019-05-09 19:23:39 +0000184 for (i = 0; i < prd->len; i++) {
185 pdesc = &prd->pdesc[i];
wdenk24711112004-04-18 22:57:51 +0000186
187 mask_in_place = pdesc->mask << pdesc->lo;
188
Jeroen Hofsteec68112f2014-07-13 23:44:21 +0200189 printf(" (%04hx:%04x) %u.",
190 mask_in_place,
191 regval & mask_in_place,
192 prd->regno);
wdenk24711112004-04-18 22:57:51 +0000193
Trent Piepho4ef32312019-05-09 19:23:39 +0000194 if (!special_field(prd->regno, pdesc, regval))
195 dump_field(pdesc, regval);
wdenk24711112004-04-18 22:57:51 +0000196 printf("\n");
197
198 }
199 printf("\n");
200}
201
202/* Special fields:
203** 0.6,13
204** 0.8
205** 2.15-0
206** 3.15-0
207** 4.4-0
208** 5.4-0
209*/
210
Trent Piepho4ef32312019-05-09 19:23:39 +0000211static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
212 ushort regval)
wdenk24711112004-04-18 22:57:51 +0000213{
Trent Piepho4ef32312019-05-09 19:23:39 +0000214 const ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
215
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500216 if ((regno == MII_BMCR) && (pdesc->lo == 6)) {
217 ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100);
wdenk24711112004-04-18 22:57:51 +0000218 printf("%2u,%2u = b%u%u speed selection = %s Mbps",
219 6, 13,
220 (regval >> 6) & 1,
221 (regval >> 13) & 1,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500222 speed_bits == BMCR_SPEED1000 ? "1000" :
223 speed_bits == BMCR_SPEED100 ? "100" :
224 "10");
wdenk24711112004-04-18 22:57:51 +0000225 return 1;
226 }
227
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500228 else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000229 dump_field(pdesc, regval);
230 printf(" = %s", ((regval >> pdesc->lo) & 1) ? "full" : "half");
wdenk24711112004-04-18 22:57:51 +0000231 return 1;
232 }
233
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500234 else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000235 dump_field(pdesc, regval);
236 printf(" = %s",
237 sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
238 sel_bits == PHY_ANLPAR_PSB_802_9 ?
239 "IEEE 802.9 ISLAN-16T" : "???");
wdenk24711112004-04-18 22:57:51 +0000240 return 1;
241 }
242
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500243 else if ((regno == MII_LPA) && (pdesc->lo == 0)) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000244 dump_field(pdesc, regval);
245 printf(" = %s",
246 sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
247 sel_bits == PHY_ANLPAR_PSB_802_9 ?
248 "IEEE 802.9 ISLAN-16T" : "???");
wdenk24711112004-04-18 22:57:51 +0000249 return 1;
250 }
251
252 return 0;
253}
254
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -0400255static char last_op[2];
256static uint last_data;
257static uint last_addr_lo;
258static uint last_addr_hi;
259static uint last_reg_lo;
260static uint last_reg_hi;
Tim Jamesa095f042015-03-25 11:55:15 +0000261static uint last_mask;
wdenk24711112004-04-18 22:57:51 +0000262
263static void extract_range(
264 char * input,
265 unsigned char * plo,
266 unsigned char * phi)
267{
268 char * end;
269 *plo = simple_strtoul(input, &end, 16);
270 if (*end == '-') {
271 end++;
272 *phi = simple_strtoul(end, NULL, 16);
273 }
274 else {
275 *phi = *plo;
276 }
277}
278
wdenk5cf91d62004-04-23 20:32:05 +0000279/* ---------------------------------------------------------------- */
Mike Frysinger3a5ee0b2010-10-20 01:06:48 -0400280static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk24711112004-04-18 22:57:51 +0000281{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200282 char op[2];
wdenk24711112004-04-18 22:57:51 +0000283 unsigned char addrlo, addrhi, reglo, reghi;
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200284 unsigned char addr, reg;
Tim Jamesa095f042015-03-25 11:55:15 +0000285 unsigned short data, mask;
wdenk24711112004-04-18 22:57:51 +0000286 int rcode = 0;
Mike Frysinger5700bb62010-07-27 18:35:08 -0400287 const char *devname;
wdenk24711112004-04-18 22:57:51 +0000288
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200289 if (argc < 2)
Simon Glass4c12eeb2011-12-10 08:44:01 +0000290 return CMD_RET_USAGE;
Shinya Kuribayashib9173af2007-12-27 15:39:54 +0900291
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500292#if defined(CONFIG_MII_INIT)
wdenk24711112004-04-18 22:57:51 +0000293 mii_init ();
294#endif
295
296 /*
297 * We use the last specified parameters, unless new ones are
298 * entered.
299 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200300 op[0] = last_op[0];
301 op[1] = last_op[1];
wdenk24711112004-04-18 22:57:51 +0000302 addrlo = last_addr_lo;
303 addrhi = last_addr_hi;
304 reglo = last_reg_lo;
305 reghi = last_reg_hi;
306 data = last_data;
Tim Jamesa095f042015-03-25 11:55:15 +0000307 mask = last_mask;
wdenk24711112004-04-18 22:57:51 +0000308
309 if ((flag & CMD_FLAG_REPEAT) == 0) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200310 op[0] = argv[1][0];
311 if (strlen(argv[1]) > 1)
312 op[1] = argv[1][1];
313 else
314 op[1] = '\0';
315
wdenk24711112004-04-18 22:57:51 +0000316 if (argc >= 3)
317 extract_range(argv[2], &addrlo, &addrhi);
318 if (argc >= 4)
319 extract_range(argv[3], &reglo, &reghi);
320 if (argc >= 5)
Tim Jamesa095f042015-03-25 11:55:15 +0000321 data = simple_strtoul(argv[4], NULL, 16);
322 if (argc >= 6)
323 mask = simple_strtoul(argv[5], NULL, 16);
wdenk24711112004-04-18 22:57:51 +0000324 }
325
Hector Palaciosfb265a72018-08-17 13:06:40 +0200326 if (addrhi > 31 && strncmp(op, "de", 2)) {
Michal Simekbdaeb8f2015-10-19 15:13:34 +0200327 printf("Incorrect PHY address. Range should be 0-31\n");
328 return CMD_RET_USAGE;
329 }
330
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200331 /* use current device */
332 devname = miiphy_get_current_dev();
333
wdenk24711112004-04-18 22:57:51 +0000334 /*
335 * check info/read/write.
336 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200337 if (op[0] == 'i') {
wdenk24711112004-04-18 22:57:51 +0000338 unsigned char j, start, end;
339 unsigned int oui;
340 unsigned char model;
341 unsigned char rev;
342
343 /*
344 * Look for any and all PHYs. Valid addresses are 0..31.
345 */
346 if (argc >= 3) {
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200347 start = addrlo; end = addrhi;
wdenk24711112004-04-18 22:57:51 +0000348 } else {
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200349 start = 0; end = 31;
wdenk24711112004-04-18 22:57:51 +0000350 }
351
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200352 for (j = start; j <= end; j++) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200353 if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
wdenk24711112004-04-18 22:57:51 +0000354 printf("PHY 0x%02X: "
355 "OUI = 0x%04X, "
356 "Model = 0x%02X, "
357 "Rev = 0x%02X, "
Larry Johnson71bc6e62007-11-01 08:46:50 -0500358 "%3dbase%s, %s\n",
wdenk24711112004-04-18 22:57:51 +0000359 j, oui, model, rev,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200360 miiphy_speed (devname, j),
Larry Johnson71bc6e62007-11-01 08:46:50 -0500361 miiphy_is_1000base_x (devname, j)
362 ? "X" : "T",
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200363 (miiphy_duplex (devname, j) == FULL)
364 ? "FDX" : "HDX");
wdenk24711112004-04-18 22:57:51 +0000365 }
366 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200367 } else if (op[0] == 'r') {
wdenk24711112004-04-18 22:57:51 +0000368 for (addr = addrlo; addr <= addrhi; addr++) {
369 for (reg = reglo; reg <= reghi; reg++) {
370 data = 0xffff;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200371 if (miiphy_read (devname, addr, reg, &data) != 0) {
wdenk24711112004-04-18 22:57:51 +0000372 printf(
373 "Error reading from the PHY addr=%02x reg=%02x\n",
374 addr, reg);
375 rcode = 1;
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200376 } else {
wdenk24711112004-04-18 22:57:51 +0000377 if ((addrlo != addrhi) || (reglo != reghi))
378 printf("addr=%02x reg=%02x data=",
379 (uint)addr, (uint)reg);
380 printf("%04X\n", data & 0x0000FFFF);
381 }
382 }
383 if ((addrlo != addrhi) && (reglo != reghi))
384 printf("\n");
385 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200386 } else if (op[0] == 'w') {
wdenk24711112004-04-18 22:57:51 +0000387 for (addr = addrlo; addr <= addrhi; addr++) {
388 for (reg = reglo; reg <= reghi; reg++) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200389 if (miiphy_write (devname, addr, reg, data) != 0) {
wdenk24711112004-04-18 22:57:51 +0000390 printf("Error writing to the PHY addr=%02x reg=%02x\n",
391 addr, reg);
392 rcode = 1;
393 }
394 }
395 }
Tim Jamesa095f042015-03-25 11:55:15 +0000396 } else if (op[0] == 'm') {
397 for (addr = addrlo; addr <= addrhi; addr++) {
398 for (reg = reglo; reg <= reghi; reg++) {
399 unsigned short val = 0;
400 if (miiphy_read(devname, addr,
401 reg, &val)) {
402 printf("Error reading from the PHY");
403 printf(" addr=%02x", addr);
404 printf(" reg=%02x\n", reg);
405 rcode = 1;
406 } else {
407 val = (val & ~mask) | (data & mask);
408 if (miiphy_write(devname, addr,
409 reg, val)) {
410 printf("Error writing to the PHY");
411 printf(" addr=%02x", addr);
412 printf(" reg=%02x\n", reg);
413 rcode = 1;
414 }
415 }
416 }
417 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200418 } else if (strncmp(op, "du", 2) == 0) {
Trent Piepho95637862019-05-09 19:23:47 +0000419 ushort regs[MII_STAT1000 + 1]; /* Last reg is 0x0a */
wdenk24711112004-04-18 22:57:51 +0000420 int ok = 1;
Trent Piepho95637862019-05-09 19:23:47 +0000421 if (reglo > MII_STAT1000 || reghi > MII_STAT1000) {
422 printf("The MII dump command only formats the standard MII registers, 0-5, 9-a.\n");
wdenk24711112004-04-18 22:57:51 +0000423 return 1;
424 }
425 for (addr = addrlo; addr <= addrhi; addr++) {
Trent Piepho4ef32312019-05-09 19:23:39 +0000426 for (reg = reglo; reg <= reghi; reg++) {
427 if (miiphy_read(devname, addr, reg,
428 &regs[reg - reglo]) != 0) {
wdenk24711112004-04-18 22:57:51 +0000429 ok = 0;
430 printf(
431 "Error reading from the PHY addr=%02x reg=%02x\n",
432 addr, reg);
433 rcode = 1;
434 }
435 }
436 if (ok)
Trent Piepho4ef32312019-05-09 19:23:39 +0000437 MII_dump(regs, reglo, reghi);
wdenk24711112004-04-18 22:57:51 +0000438 printf("\n");
439 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200440 } else if (strncmp(op, "de", 2) == 0) {
441 if (argc == 2)
442 miiphy_listdev ();
443 else
444 miiphy_set_current_dev (argv[2]);
wdenk24711112004-04-18 22:57:51 +0000445 } else {
Simon Glass4c12eeb2011-12-10 08:44:01 +0000446 return CMD_RET_USAGE;
wdenk24711112004-04-18 22:57:51 +0000447 }
448
449 /*
450 * Save the parameters for repeats.
451 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200452 last_op[0] = op[0];
453 last_op[1] = op[1];
wdenk24711112004-04-18 22:57:51 +0000454 last_addr_lo = addrlo;
455 last_addr_hi = addrhi;
456 last_reg_lo = reglo;
457 last_reg_hi = reghi;
458 last_data = data;
Tim Jamesa095f042015-03-25 11:55:15 +0000459 last_mask = mask;
wdenk24711112004-04-18 22:57:51 +0000460
461 return rcode;
462}
463
464/***************************************************/
465
466U_BOOT_CMD(
Tim Jamesa095f042015-03-25 11:55:15 +0000467 mii, 6, 1, do_mii,
Peter Tyser2fb26042009-01-27 18:03:12 -0600468 "MII utility commands",
Tim Jamesa095f042015-03-25 11:55:15 +0000469 "device - list available devices\n"
470 "mii device <devname> - set current device\n"
471 "mii info <addr> - display MII PHY info\n"
472 "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
473 "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
474 "mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
475 " updating bits identified in <mask>\n"
476 "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200477 "Addr and/or reg may be ranges, e.g. 2-7."
wdenk24711112004-04-18 22:57:51 +0000478);