blob: 94e0ddbd885ea7ce0c6322242282fa011ca81221 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sunee52b182012-10-11 07:13:37 +00002/*
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
York Sunee52b182012-10-11 07:13:37 +00004 */
5
6/*
7 * T4240 QDS board configuration file
8 */
York Sun1cb19fb2013-06-27 10:48:29 -07009#ifndef __CONFIG_H
10#define __CONFIG_H
11
York Sunee52b182012-10-11 07:13:37 +000012#define CONFIG_FSL_SATA_V2
13#define CONFIG_PCIE4
14
15#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
16
York Sun1cb19fb2013-06-27 10:48:29 -070017#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090018#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
Miquel Raynal88718be2019-10-03 19:50:03 +020019#if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD)
Shaohui Xieb6036992014-04-22 15:10:44 +080020#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
21#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22#else
Shaohui Xieb6036992014-04-22 15:10:44 +080023#define CONFIG_SPL_FLUSH_IMAGE
Shaohui Xieb6036992014-04-22 15:10:44 +080024#define CONFIG_SPL_PAD_TO 0x40000
25#define CONFIG_SPL_MAX_SIZE 0x28000
26#define RESET_VECTOR_OFFSET 0x27FFC
27#define BOOT_PAGE_OFFSET 0x27000
28
Miquel Raynal88718be2019-10-03 19:50:03 +020029#ifdef CONFIG_MTD_RAW_NAND
Shaohui Xieb6036992014-04-22 15:10:44 +080030#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
31#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
32#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
33#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
Zhao Qiangec90ac72016-09-08 12:55:32 +080034#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
York Sun1cb19fb2013-06-27 10:48:29 -070035#endif
36
Shaohui Xieb6036992014-04-22 15:10:44 +080037#ifdef CONFIG_SDCARD
38#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shaohui Xieb6036992014-04-22 15:10:44 +080039#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
40#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
41#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
42#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
43#ifndef CONFIG_SPL_BUILD
44#define CONFIG_SYS_MPC85XX_NO_RESETVEC
45#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080046#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
Shaohui Xieb6036992014-04-22 15:10:44 +080047#endif
48
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_SKIP_RELOCATE
51#define CONFIG_SPL_COMMON_INIT_DDR
52#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Shaohui Xieb6036992014-04-22 15:10:44 +080053#endif
54
55#endif
56#endif /* CONFIG_RAMBOOT_PBL */
57
York Sun1cb19fb2013-06-27 10:48:29 -070058#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
59/* Set 1M boot space */
60#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
61#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
62 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
63#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
York Sun1cb19fb2013-06-27 10:48:29 -070064#endif
65
66#define CONFIG_SRIO_PCIE_BOOT_MASTER
67#define CONFIG_DDR_ECC
68
York Sunee52b182012-10-11 07:13:37 +000069#include "t4qds.h"
York Sun1cb19fb2013-06-27 10:48:29 -070070
York Sun1cb19fb2013-06-27 10:48:29 -070071#if defined(CONFIG_SPIFLASH)
York Sun1cb19fb2013-06-27 10:48:29 -070072#elif defined(CONFIG_SDCARD)
York Sun1cb19fb2013-06-27 10:48:29 -070073#define CONFIG_SYS_MMC_ENV_DEV 0
York Sun1cb19fb2013-06-27 10:48:29 -070074#endif
75
76#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
77#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
78
79#ifndef __ASSEMBLY__
80unsigned long get_board_sys_clk(void);
81unsigned long get_board_ddr_clk(void);
82#endif
83
84/* EEPROM */
85#define CONFIG_ID_EEPROM
86#define CONFIG_SYS_I2C_EEPROM_NXID
87#define CONFIG_SYS_EEPROM_BUS_NUM 0
88#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
89#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
90
91/*
92 * DDR Setup
93 */
94#define CONFIG_SYS_SPD_BUS_NUM 0
95#define SPD_EEPROM_ADDRESS1 0x51
96#define SPD_EEPROM_ADDRESS2 0x52
97#define SPD_EEPROM_ADDRESS3 0x53
98#define SPD_EEPROM_ADDRESS4 0x54
99#define SPD_EEPROM_ADDRESS5 0x55
100#define SPD_EEPROM_ADDRESS6 0x56
101#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
102#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
103
104/*
105 * IFC Definitions
106 */
107#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
108#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
109 + 0x8000000) | \
110 CSPR_PORT_SIZE_16 | \
111 CSPR_MSEL_NOR | \
112 CSPR_V)
113#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
114#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
115 CSPR_PORT_SIZE_16 | \
116 CSPR_MSEL_NOR | \
117 CSPR_V)
118#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
119/* NOR Flash Timing Params */
120#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
121
122#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
123 FTIM0_NOR_TEADC(0x5) | \
124 FTIM0_NOR_TEAHC(0x5))
125#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
126 FTIM1_NOR_TRAD_NOR(0x1A) |\
127 FTIM1_NOR_TSEQRAD_NOR(0x13))
128#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
129 FTIM2_NOR_TCH(0x4) | \
130 FTIM2_NOR_TWPH(0x0E) | \
131 FTIM2_NOR_TWP(0x1c))
132#define CONFIG_SYS_NOR_FTIM3 0x0
133
134#define CONFIG_SYS_FLASH_QUIET_TEST
135#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
136
137#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
138#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
139#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
140#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
141
142#define CONFIG_SYS_FLASH_EMPTY_INFO
143#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
144 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
145
146#define CONFIG_FSL_QIXIS /* use common QIXIS code */
147#define QIXIS_BASE 0xffdf0000
148#define QIXIS_LBMAP_SWITCH 6
149#define QIXIS_LBMAP_MASK 0x0f
150#define QIXIS_LBMAP_SHIFT 0
151#define QIXIS_LBMAP_DFLTBANK 0x00
152#define QIXIS_LBMAP_ALTBANK 0x04
153#define QIXIS_RST_CTL_RESET 0x83
York Sunc63e1372013-06-25 11:37:48 -0700154#define QIXIS_RST_FORCE_MEM 0x1
York Sun1cb19fb2013-06-27 10:48:29 -0700155#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
156#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
157#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800158#define QIXIS_BRDCFG5 0x55
159#define QIXIS_MUX_SDHC 2
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800160#define QIXIS_MUX_SDHC_WIDTH8 1
York Sun1cb19fb2013-06-27 10:48:29 -0700161#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
162
163#define CONFIG_SYS_CSPR3_EXT (0xf)
164#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
165 | CSPR_PORT_SIZE_8 \
166 | CSPR_MSEL_GPCM \
167 | CSPR_V)
Rajesh Bhagat088d52c2018-11-05 18:01:19 +0000168#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
York Sun1cb19fb2013-06-27 10:48:29 -0700169#define CONFIG_SYS_CSOR3 0x0
170/* QIXIS Timing parameters for IFC CS3 */
171#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
172 FTIM0_GPCM_TEADC(0x0e) | \
173 FTIM0_GPCM_TEAHC(0x0e))
174#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
175 FTIM1_GPCM_TRAD(0x3f))
176#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800177 FTIM2_GPCM_TCH(0x8) | \
York Sun1cb19fb2013-06-27 10:48:29 -0700178 FTIM2_GPCM_TWP(0x1f))
179#define CONFIG_SYS_CS3_FTIM3 0x0
180
181/* NAND Flash on IFC */
182#define CONFIG_NAND_FSL_IFC
183#define CONFIG_SYS_NAND_BASE 0xff800000
184#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
185
186#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
187#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
188 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
189 | CSPR_MSEL_NAND /* MSEL = NAND */ \
190 | CSPR_V)
191#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
192
193#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
194 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
195 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
196 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
197 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
198 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
199 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
200
201#define CONFIG_SYS_NAND_ONFI_DETECTION
202
203/* ONFI NAND Flash mode0 Timing Params */
204#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
205 FTIM0_NAND_TWP(0x18) | \
206 FTIM0_NAND_TWCHT(0x07) | \
207 FTIM0_NAND_TWH(0x0a))
208#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
209 FTIM1_NAND_TWBE(0x39) | \
210 FTIM1_NAND_TRR(0x0e) | \
211 FTIM1_NAND_TRP(0x18))
212#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
213 FTIM2_NAND_TREH(0x0a) | \
214 FTIM2_NAND_TWHRE(0x1e))
215#define CONFIG_SYS_NAND_FTIM3 0x0
216
217#define CONFIG_SYS_NAND_DDR_LAW 11
218
219#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
220#define CONFIG_SYS_MAX_NAND_DEVICE 1
York Sun1cb19fb2013-06-27 10:48:29 -0700221
222#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Prabhakar Kushwaha68ec9c82013-10-04 13:47:58 +0530223#define CONFIG_SYS_NAND_MAX_OOBFREE 2
224#define CONFIG_SYS_NAND_MAX_ECCPOS 256
York Sun1cb19fb2013-06-27 10:48:29 -0700225
Miquel Raynal88718be2019-10-03 19:50:03 +0200226#if defined(CONFIG_MTD_RAW_NAND)
York Sun1cb19fb2013-06-27 10:48:29 -0700227#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
228#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
229#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
230#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
231#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
232#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
233#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
234#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
Shaohui Xieb6036992014-04-22 15:10:44 +0800235#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
236#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
237#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
238#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
239#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
240#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
241#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
242#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
243#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
244#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
York Sun1cb19fb2013-06-27 10:48:29 -0700245#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
246#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
247#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
248#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
249#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
250#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
251#else
252#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
253#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
254#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
255#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
256#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
257#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
258#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
259#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Shaohui Xieb6036992014-04-22 15:10:44 +0800260#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
261#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
262#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
263#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
264#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
265#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
266#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
267#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
York Sun1cb19fb2013-06-27 10:48:29 -0700268#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
269#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
270#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
271#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
272#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
273#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
274#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
275#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
276#endif
York Sun1cb19fb2013-06-27 10:48:29 -0700277
278#if defined(CONFIG_RAMBOOT_PBL)
279#define CONFIG_SYS_RAMBOOT
280#endif
281
York Sun1cb19fb2013-06-27 10:48:29 -0700282/* I2C */
283#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
284#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
285#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
286#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
287
288#define I2C_MUX_CH_DEFAULT 0x8
289#define I2C_MUX_CH_VOL_MONITOR 0xa
290#define I2C_MUX_CH_VSC3316_FS 0xc
291#define I2C_MUX_CH_VSC3316_BS 0xd
292
293/* Voltage monitor on channel 2*/
294#define I2C_VOL_MONITOR_ADDR 0x40
295#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
296#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
297#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
298
299/* VSC Crossbar switches */
300#define CONFIG_VSC_CROSSBAR
301#define VSC3316_FSM_TX_ADDR 0x70
302#define VSC3316_FSM_RX_ADDR 0x71
303
304/*
305 * RapidIO
306 */
307
308/*
309 * for slave u-boot IMAGE instored in master memory space,
310 * PHYS must be aligned based on the SIZE
311 */
Liu Gange4911812014-05-15 14:30:34 +0800312#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
313#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
314#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
315#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
York Sun1cb19fb2013-06-27 10:48:29 -0700316/*
317 * for slave UCODE and ENV instored in master memory space,
318 * PHYS must be aligned based on the SIZE
319 */
Liu Gange4911812014-05-15 14:30:34 +0800320#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
York Sun1cb19fb2013-06-27 10:48:29 -0700321#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
322#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
323
324/* slave core release by master*/
325#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
326#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
327
328/*
329 * SRIO_PCIE_BOOT - SLAVE
330 */
331#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
332#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
333#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
334 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
335#endif
336/*
337 * eSPI - Enhanced SPI
338 */
York Sun1cb19fb2013-06-27 10:48:29 -0700339
York Sun1cb19fb2013-06-27 10:48:29 -0700340/* Qman/Bman */
341#ifndef CONFIG_NOBQFMAN
York Sun1cb19fb2013-06-27 10:48:29 -0700342#define CONFIG_SYS_BMAN_NUM_PORTALS 50
343#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
344#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
345#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500346#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
347#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
348#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
349#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
350#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
351 CONFIG_SYS_BMAN_CENA_SIZE)
352#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
353#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
York Sun1cb19fb2013-06-27 10:48:29 -0700354#define CONFIG_SYS_QMAN_NUM_PORTALS 50
355#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
356#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
357#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500358#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
359#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
360#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
361#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
362#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
363 CONFIG_SYS_QMAN_CENA_SIZE)
364#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
365#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
York Sun1cb19fb2013-06-27 10:48:29 -0700366
367#define CONFIG_SYS_DPAA_FMAN
368#define CONFIG_SYS_DPAA_PME
369#define CONFIG_SYS_PMAN
370#define CONFIG_SYS_DPAA_DCE
Minghuan Lian0795eff2013-07-03 18:32:41 +0800371#define CONFIG_SYS_DPAA_RMAN
York Sun1cb19fb2013-06-27 10:48:29 -0700372#define CONFIG_SYS_INTERLAKEN
373
374/* Default address of microcode for the Linux Fman driver */
375#if defined(CONFIG_SPIFLASH)
376/*
377 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
378 * env, so we got 0x110000.
379 */
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800380#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
York Sun1cb19fb2013-06-27 10:48:29 -0700381#elif defined(CONFIG_SDCARD)
382/*
383 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shaohui Xieb6036992014-04-22 15:10:44 +0800384 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
385 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
York Sun1cb19fb2013-06-27 10:48:29 -0700386 */
Shaohui Xieb6036992014-04-22 15:10:44 +0800387#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Miquel Raynal88718be2019-10-03 19:50:03 +0200388#elif defined(CONFIG_MTD_RAW_NAND)
Shaohui Xieb6036992014-04-22 15:10:44 +0800389#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
York Sun1cb19fb2013-06-27 10:48:29 -0700390#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
391/*
392 * Slave has no ucode locally, it can fetch this from remote. When implementing
393 * in two corenet boards, slave's ucode could be stored in master's memory
394 * space, the address can be mapped from slave TLB->slave LAW->
395 * slave SRIO or PCIE outbound window->master inbound window->
396 * master LAW->the ucode address in master's memory space.
397 */
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800398#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
York Sun1cb19fb2013-06-27 10:48:29 -0700399#else
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800400#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
York Sun1cb19fb2013-06-27 10:48:29 -0700401#endif
402#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
403#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
404#endif /* CONFIG_NOBQFMAN */
405
406#ifdef CONFIG_SYS_DPAA_FMAN
York Sun1cb19fb2013-06-27 10:48:29 -0700407#define CONFIG_PHYLIB_10G
408#define CONFIG_PHY_VITESSE
409#define CONFIG_PHY_TERANETICS
410#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
411#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
412#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
413#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
414#define FM1_10GEC1_PHY_ADDR 0x0
415#define FM1_10GEC2_PHY_ADDR 0x1
416#define FM2_10GEC1_PHY_ADDR 0x2
417#define FM2_10GEC2_PHY_ADDR 0x3
418#endif
419
York Sun1cb19fb2013-06-27 10:48:29 -0700420/* SATA */
421#ifdef CONFIG_FSL_SATA_V2
York Sun1cb19fb2013-06-27 10:48:29 -0700422#define CONFIG_SYS_SATA_MAX_DEVICE 2
423#define CONFIG_SATA1
424#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
425#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
426#define CONFIG_SATA2
427#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
428#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
429
430#define CONFIG_LBA48
York Sun1cb19fb2013-06-27 10:48:29 -0700431#endif
432
433#ifdef CONFIG_FMAN_ENET
York Sun1cb19fb2013-06-27 10:48:29 -0700434#define CONFIG_ETHPRIME "FM1@DTSEC1"
York Sun1cb19fb2013-06-27 10:48:29 -0700435#endif
436
437/*
438* USB
439*/
York Sun1cb19fb2013-06-27 10:48:29 -0700440#define CONFIG_USB_EHCI_FSL
441#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
York Sun1cb19fb2013-06-27 10:48:29 -0700442#define CONFIG_HAS_FSL_DR_USB
443
York Sun1cb19fb2013-06-27 10:48:29 -0700444#ifdef CONFIG_MMC
York Sun1cb19fb2013-06-27 10:48:29 -0700445#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
446#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Haijun.Zhangef38f3f2013-10-31 09:38:19 +0800447#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800448#define CONFIG_ESDHC_DETECT_QUIRK \
449 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
450 IS_SVR_REV(get_svr(), 1, 0))
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800451#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
452 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
York Sun1cb19fb2013-06-27 10:48:29 -0700453#endif
454
York Sun1cb19fb2013-06-27 10:48:29 -0700455
456#define __USB_PHY_TYPE utmi
457
458/*
459 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
460 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
461 * interleaving. It can be cacheline, page, bank, superbank.
462 * See doc/README.fsl-ddr for details.
463 */
York Sun26bc57d2016-11-21 13:35:41 -0800464#ifdef CONFIG_ARCH_T4240
York Sun1cb19fb2013-06-27 10:48:29 -0700465#define CTRL_INTLV_PREFERED 3way_4KB
466#else
467#define CTRL_INTLV_PREFERED cacheline
468#endif
469
470#define CONFIG_EXTRA_ENV_SETTINGS \
471 "hwconfig=fsl_ddr:" \
472 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
473 "bank_intlv=auto;" \
474 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
475 "netdev=eth0\0" \
476 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
477 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
478 "tftpflash=tftpboot $loadaddr $uboot && " \
479 "protect off $ubootaddr +$filesize && " \
480 "erase $ubootaddr +$filesize && " \
481 "cp.b $loadaddr $ubootaddr $filesize && " \
482 "protect on $ubootaddr +$filesize && " \
483 "cmp.b $loadaddr $ubootaddr $filesize\0" \
484 "consoledev=ttyS0\0" \
485 "ramdiskaddr=2000000\0" \
486 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500487 "fdtaddr=1e00000\0" \
York Sun1cb19fb2013-06-27 10:48:29 -0700488 "fdtfile=t4240qds/t4240qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500489 "bdev=sda3\0"
York Sun1cb19fb2013-06-27 10:48:29 -0700490
491#define CONFIG_HVBOOT \
492 "setenv bootargs config-addr=0x60000000; " \
493 "bootm 0x01000000 - 0x00f00000"
494
495#define CONFIG_ALU \
496 "setenv bootargs root=/dev/$bdev rw " \
497 "console=$consoledev,$baudrate $othbootargs;" \
498 "cpu 1 release 0x01000000 - - -;" \
499 "cpu 2 release 0x01000000 - - -;" \
500 "cpu 3 release 0x01000000 - - -;" \
501 "cpu 4 release 0x01000000 - - -;" \
502 "cpu 5 release 0x01000000 - - -;" \
503 "cpu 6 release 0x01000000 - - -;" \
504 "cpu 7 release 0x01000000 - - -;" \
505 "go 0x01000000"
506
507#define CONFIG_LINUX \
508 "setenv bootargs root=/dev/ram rw " \
509 "console=$consoledev,$baudrate $othbootargs;" \
510 "setenv ramdiskaddr 0x02000000;" \
511 "setenv fdtaddr 0x00c00000;" \
512 "setenv loadaddr 0x1000000;" \
513 "bootm $loadaddr $ramdiskaddr $fdtaddr"
514
515#define CONFIG_HDBOOT \
516 "setenv bootargs root=/dev/$bdev rw " \
517 "console=$consoledev,$baudrate $othbootargs;" \
518 "tftp $loadaddr $bootfile;" \
519 "tftp $fdtaddr $fdtfile;" \
520 "bootm $loadaddr - $fdtaddr"
521
522#define CONFIG_NFSBOOTCOMMAND \
523 "setenv bootargs root=/dev/nfs rw " \
524 "nfsroot=$serverip:$rootpath " \
525 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
526 "console=$consoledev,$baudrate $othbootargs;" \
527 "tftp $loadaddr $bootfile;" \
528 "tftp $fdtaddr $fdtfile;" \
529 "bootm $loadaddr - $fdtaddr"
530
531#define CONFIG_RAMBOOTCOMMAND \
532 "setenv bootargs root=/dev/ram rw " \
533 "console=$consoledev,$baudrate $othbootargs;" \
534 "tftp $ramdiskaddr $ramdiskfile;" \
535 "tftp $loadaddr $bootfile;" \
536 "tftp $fdtaddr $fdtfile;" \
537 "bootm $loadaddr $ramdiskaddr $fdtaddr"
538
539#define CONFIG_BOOTCOMMAND CONFIG_LINUX
540
York Sun1cb19fb2013-06-27 10:48:29 -0700541#include <asm/fsl_secure_boot.h>
York Sun1cb19fb2013-06-27 10:48:29 -0700542
543#endif /* __CONFIG_H */