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wdenkc7de8292002-11-19 11:04:11 +00001/*
2 * (C) Copyright 2002
3 * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23#include <common.h>
24#include <pci.h>
25#include <ata.h>
26#include "memio.h"
27#include "articiaS.h"
28#include "via686.h"
29#include "i8259.h"
30
31#undef VIA_DEBUG
32
33#ifdef VIA_DEBUG
34#define PRINTF(fmt,args...) printf (fmt ,##args)
35#else
36#define PRINTF(fmt,args...)
37#endif
38
39
40/* Setup the ISA-to-PCI host bridge */
41void via_isa_init(pci_dev_t dev, struct pci_config_table *table)
42{
43 char regval;
44 if (PCI_FUNC(dev) == 0)
45 {
46 PRINTF("... PCI-to-ISA bridge, dev=0x%X\n", dev);
47
48 /* Enable I/O Recovery time */
49 pci_write_config_byte(dev, 0x40, 0x08);
50
51 /* Enable ISA refresh */
52 pci_write_config_byte(dev, 0x41, 0x41); /* was 01 */
53
54 /* Enable ISA line buffer */
55 pci_write_config_byte(dev, 0x45, 0x80);
56
57 /* Gate INTR, and flush line buffer */
58 pci_write_config_byte(dev, 0x46, 0x60);
59
60 /* Enable EISA ports 4D0/4D1. Do we need this ? */
61 pci_write_config_byte(dev, 0x47, 0xe6); /* was 20 */
62
63 /* 512 K PCI Decode */
64 pci_write_config_byte(dev, 0x48, 0x01);
65
66 /* Wait for PGNT before grant to ISA Master/DMA */
67 /* ports 0-FF to SDBus */
68 /* IRQ 14 and 15 for ide 0/1 */
69 pci_write_config_byte(dev, 0x4a, 0x04); /* Was c4 */
70
71 /* Plug'n'Play */
72 /* Parallel DRQ 3, Floppy DRQ 2 (default) */
73 pci_write_config_byte(dev, 0x50, 0x0e);
74
75 /* IRQ Routing for Floppy and Parallel port */
76 /* IRQ 6 for floppy, IRQ 7 for parallel port */
77 pci_write_config_byte(dev, 0x51, 0x76);
78
79 /* IRQ Routing for serial ports (take IRQ 3 and 4) */
80 pci_write_config_byte(dev, 0x52, 0x34);
81
82 /* All IRQ's level triggered. */
83 pci_write_config_byte(dev, 0x54, 0x00);
84
85 /* PCI IRQ's all at IRQ 9 */
86 pci_write_config_byte(dev, 0x55, 0x90);
87 pci_write_config_byte(dev, 0x56, 0x99);
88 pci_write_config_byte(dev, 0x57, 0x90);
89
90 /* Enable Keyboard */
91 pci_read_config_byte(dev, 0x5A, &regval);
92 regval |= 0x01;
93 pci_write_config_byte(dev, 0x5A, regval);
94
95 pci_write_config_byte(dev, 0x80, 0);
96 pci_write_config_byte(dev, 0x85, 0x01);
97
98/* pci_write_config_byte(dev, 0x77, 0x00); */
99 }
100}
101
102/*
103 * Initialize PNP irq routing
104 */
105
106void via_init_irq_routing(uint8 irq_map[])
107{
108 char *s;
109 uint8 level_edge_bits = 0xf;
110
111 /* Set irq routings */
112 pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4);
113 pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4);
114 pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4);
115
116 /*
117 * Gather level/edge bits
118 * Default is to assume level triggered
119 */
120
121 s = getenv("pci_irqa_select");
122 if (s && strcmp(s, "level") == 0)
123 level_edge_bits &= ~0x01;
124
125 s = getenv("pci_irqb_select");
126 if (s && strcmp(s, "level") == 0)
127 level_edge_bits &= ~0x02;
128
129 s = getenv("pci_irqc_select");
130 if (s && strcmp(s, "level") == 0)
131 level_edge_bits &= ~0x04;
132
133 s = getenv("pci_irqd_select");
134 if (s && strcmp(s, "level") == 0)
135 level_edge_bits &= ~0x08;
136
137 PRINTF("IRQ map\n");
138 PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level");
139 PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level");
140 PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level");
141 PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level");
142 pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits);
143
144 PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54),
145 pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56),
146 pci_read_cfg_byte(0, 7<<3, 0x57));
147}
148
149
150/* Setup the IDE controller. This doesn't seem to work yet. I/O to an IDE controller port */
151/* always return the last character output on the serial port (!) */
152/* This function is called by the pnp-library when it encounters 0:7:1 */
153void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
154{
155 PRINTF("... IDE controller, dev=0x%X\n", dev);
156
157 /* Enable both IDE channels. */
158 pci_write_config_byte(dev, 0x40, 0x03);
159 /* udelay(10000); */
160 /* udelay(10000); */
161
162 /* Enable IO Space */
163 pci_write_config_word(dev, 0x04, 0x03);
164
165 /* Set to compatibility mode */
166 pci_write_config_byte(dev, 0x09, 0x8A); /* WAS: 0x8f); */
167
168 /* Set to legacy interrupt mode */
169 pci_write_config_byte(dev, 0x3d, 0x00); /* WAS: 0x01); */
170
171}
172
173
174/* Set the base address of the floppy controller to 0x3F0 */
175void via_fdc_init(pci_dev_t dev)
176{
177 unsigned char c;
178 /* Enable Configuration mode */
179 pci_read_config_byte(dev, 0x85, &c);
180 c |= 0x02;
181 pci_write_config_byte(dev, 0x85, c);
182
183 /* Set floppy controller port to 0x3F0. */
184 SIO_WRITE_CONFIG(0xE3, (0x3F<<2));
185
186 /* Enable floppy controller */
187 SIO_READ_CONFIG(0xE2, c);
188 c |= 0x10;
189 SIO_WRITE_CONFIG(0xE2, c);
190
191 /* Switch of configuration mode */
192 pci_read_config_byte(dev, 0x85, &c);
193 c &= ~0x02;
194 pci_write_config_byte(dev, 0x85, c);
195}
196
197/* Init function 0 of the via southbridge. Called by the pnp-library */
198void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
199{
200 if (PCI_FUNC(dev) == 0)
201 {
202 /* FIXME: Try to generate a PCI reset */
203 /* unsigned char c; */
204 /* pci_read_config_byte(dev, 0x47, &c); */
205 /* pci_write_config_byte(dev, 0x47, c | 0x01); */
206
207 via_isa_init(dev, table);
208 via_fdc_init(dev);
209 }
210}
211
212__asm (" .globl via_calibrate_time_base \n"
213 "via_calibrate_time_base: \n"
wdenk8bde7f72003-06-27 21:31:46 +0000214 " lis 9, 0xfe00 \n"
215 " li 0, 0x00 \n"
wdenkc7de8292002-11-19 11:04:11 +0000216 " mttbu 0 \n"
217 " mttbl 0 \n"
218 "ctb_loop: \n"
wdenk8bde7f72003-06-27 21:31:46 +0000219 " lbz 0, 0x61(9) \n"
220 " eieio \n"
221 " andi. 0, 0, 0x20 \n"
222 " beq ctb_loop \n"
223 "ctb_done: \n"
224 " mftb 3 \n"
225 " blr");
wdenkc7de8292002-11-19 11:04:11 +0000226
227extern unsigned long via_calibrate_time_base(void);
228
229void via_calibrate_bus_freq(void)
230{
231 DECLARE_GLOBAL_DATA_PTR;
232
233 unsigned long tb;
234
235 /* This is 20 microseconds */
236 #define CALIBRATE_TIME 28636
237
238
239 /* Enable the timer (and disable speaker) */
240 unsigned char c;
241 c = in_byte(0x61);
242 out_byte(0x61, ((c & ~0x02) | 0x01));
243
244 /* Set timer 2 to low/high writing */
245 out_byte(0x43, 0xb0);
246 out_byte(0x42, CALIBRATE_TIME & 0xff);
247 out_byte(0x42, CALIBRATE_TIME >>8);
248
249 /* Read the time base */
250 tb = via_calibrate_time_base();
251
252 if (tb >= 700000)
253 gd->bus_clk = 133333333;
254 else
255 gd->bus_clk = 100000000;
256
257}
258
259
260void ide_led(uchar led, uchar status)
261{
262/* unsigned char c = in_byte(0x92); */
263
264/* if (!status) */
265/* out_byte(0x92, c | 0xC0); */
266/* else */
267/* out_byte(0x92, c & ~0xC0); */
268}
269
270
271void via_init_afterscan(void)
272{
273 /* Modify IDE controller setup */
274 pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20);
275 pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
276 pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff);
277 pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b); /* FIXME: Might depend on drives connected */
278 pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42); /* FIXME: Might depend on drives connected */
279 pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05);
280 pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18);
281 pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10);
282 pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22); /* FIXME: Not documented, but set in PC bios */
283 pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20); /* FIXME: Not documented */
284
285 /* Modify some values in the USB controller */
286 pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17);
287 pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01);
288 pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12);
289 pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03);
290 pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40);
291
292 pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17);
293 pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01);
294 pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12);
295 pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03);
296 pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40);
297
298
299}