blob: 070dbf62c49f7ac503afc35f0feafe858fefe8bb [file] [log] [blame]
Wolfgang Denk0e4018d2005-09-26 01:14:38 +02001/*
2 * (C) Copyright 2001
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2001
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
9 * ebenard@eukrea.com
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
31#include <linux/byteorder/swab.h>
32
33#define CFG_MAX_FLASH_BANKS 1
34#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
35
36flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
37
38#define FLASH_PORT_WIDTH ushort
39#define FLASH_PORT_WIDTHV vu_short
40#define SWAP(x) __swab16(x)
41
42#define FPW FLASH_PORT_WIDTH
43#define FPWV FLASH_PORT_WIDTHV
44
45#define mb() __asm__ __volatile__ ("" : : : "memory")
46
47/* Intel-compatible flash commands */
48#define INTEL_PROGRAM 0x00100010
49#define INTEL_ERASE 0x00200020
50#define INTEL_PROG 0x00400040
51#define INTEL_CLEAR 0x00500050
52#define INTEL_LOCKBIT 0x00600060
53#define INTEL_PROTECT 0x00010001
54#define INTEL_STATUS 0x00700070
55#define INTEL_READID 0x00900090
56#define INTEL_SUSPEND 0x00B000B0
57#define INTEL_CONFIRM 0x00D000D0
58#define INTEL_RESET 0xFFFFFFFF
59
60/* Intel-compatible flash status bits */
61#define INTEL_FINISHED 0x00800080
62#define INTEL_OK 0x00800080
63
64/*-----------------------------------------------------------------------
65 * Functions
66 */
67static ulong flash_get_size (FPW *addr, flash_info_t *info);
68static int write_data (flash_info_t *info, ulong dest, FPW data);
69static void flash_get_offsets (ulong base, flash_info_t *info);
70void inline spin_wheel (void);
71
72/*-----------------------------------------------------------------------
73 */
74
75unsigned long flash_init (void)
76{
77 int i;
78 ulong size = 0;
79
80 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
81 switch (i) {
82 case 0:
83 flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
84 flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
85 break;
86 default:
87 panic ("configured too many flash banks!\n");
88 break;
89 }
90 size += flash_info[i].size;
91 }
92
93 /* Protect monitor and environment sectors
94 */
95 flash_protect ( FLAG_PROTECT_SET,
96 CFG_FLASH_BASE,
97 CFG_FLASH_BASE + monitor_flash_len - 1,
98 &flash_info[0] );
99
100 flash_protect ( FLAG_PROTECT_SET,
101 CFG_ENV_ADDR,
102 CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
103
104 return size;
105}
106
107/*-----------------------------------------------------------------------
108 */
109static void flash_get_offsets (ulong base, flash_info_t *info)
110{
111 int i;
112
113 if (info->flash_id == FLASH_UNKNOWN) {
114 return;
115 }
116
117 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
118 for (i = 0; i < info->sector_count; i++) {
119 info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
120 info->protect[i] = 0;
121 }
122 }
123}
124
125/*-----------------------------------------------------------------------
126 */
127void flash_print_info (flash_info_t *info)
128{
129 int i;
130
131 if (info->flash_id == FLASH_UNKNOWN) {
132 printf ("missing or unknown FLASH type\n");
133 return;
134 }
135
136 switch (info->flash_id & FLASH_VENDMASK) {
137 case FLASH_MAN_INTEL:
138 printf ("INTEL ");
139 break;
140 default:
141 printf ("Unknown Vendor ");
142 break;
143 }
144
145 switch (info->flash_id & FLASH_TYPEMASK) {
146 case FLASH_28F640J3A:
147 printf ("28F640J3A\n");
148 break;
149 case FLASH_28F128J3A:
150 printf ("28F128J3A\n");
151 break;
152 default:
153 printf ("Unknown Chip Type\n");
154 break;
155 }
156
157 printf (" Size: %ld MB in %d Sectors\n",
158 info->size >> 20, info->sector_count);
159
160 printf (" Sector Start Addresses:");
161 for (i = 0; i < info->sector_count; ++i) {
162 if ((i % 5) == 0)
163 printf ("\n ");
164 printf (" %08lX%s",
165 info->start[i],
166 info->protect[i] ? " (RO)" : " ");
167 }
168 printf ("\n");
169 return;
170}
171
172/*
173 * The following code cannot be run from FLASH!
174 */
175static ulong flash_get_size (FPW *addr, flash_info_t *info)
176{
177 volatile FPW value;
178
179 /* Write auto select command: read Manufacturer ID */
180 addr[0x5555] = (FPW) 0x00AA00AA;
181 addr[0x2AAA] = (FPW) 0x00550055;
182 addr[0x5555] = (FPW) 0x00900090;
183
184 mb ();
185 value = addr[0];
186
187 switch (value) {
188
189 case (FPW) INTEL_MANUFACT:
190 info->flash_id = FLASH_MAN_INTEL;
191 break;
192
193 default:
194 info->flash_id = FLASH_UNKNOWN;
195 info->sector_count = 0;
196 info->size = 0;
197 addr[0] = (FPW) INTEL_RESET; /* restore read mode */
198 return (0); /* no or unknown flash */
199 }
200
201 mb ();
202 value = addr[1]; /* device ID */
203
204 switch (value) {
205
206 case (FPW) INTEL_ID_28F640J3A:
207 info->flash_id += FLASH_28F640J3A;
208 info->sector_count = 64;
209 info->size = 0x00800000;
210 break; /* => 8 MB */
211
212 case (FPW) INTEL_ID_28F128J3A:
213 info->flash_id += FLASH_28F128J3A;
214 info->sector_count = 128;
215 info->size = 0x01000000;
216 break; /* => 16 MB */
217
218 default:
219 info->flash_id = FLASH_UNKNOWN;
220 break;
221 }
222
223 if (info->sector_count > CFG_MAX_FLASH_SECT) {
224 printf ("** ERROR: sector count %d > max (%d) **\n",
225 info->sector_count, CFG_MAX_FLASH_SECT);
226 info->sector_count = CFG_MAX_FLASH_SECT;
227 }
228
229 addr[0] = (FPW) INTEL_RESET; /* restore read mode */
230
231 return (info->size);
232}
233
234
235/*-----------------------------------------------------------------------
236 */
237
238int flash_erase (flash_info_t *info, int s_first, int s_last)
239{
240 int flag, prot, sect;
241 ulong type, start, last;
242 int rcode = 0;
243 int cflag, iflag;
244
245 if ((s_first < 0) || (s_first > s_last)) {
246 if (info->flash_id == FLASH_UNKNOWN) {
247 printf ("- missing\n");
248 } else {
249 printf ("- no sectors to erase\n");
250 }
251 return 1;
252 }
253
254 type = (info->flash_id & FLASH_VENDMASK);
255 if ((type != FLASH_MAN_INTEL)) {
256 printf ("Can't erase unknown flash type %08lx - aborted\n",
257 info->flash_id);
258 return 1;
259 }
260
261 prot = 0;
262 for (sect = s_first; sect <= s_last; ++sect) {
263 if (info->protect[sect]) {
264 prot++;
265 }
266 }
267
268 if (prot) {
269 printf ("- Warning: %d protected sectors will not be erased!\n",
270 prot);
271 } else {
272 printf ("\n");
273 }
274
275 start = get_timer (0);
276 last = start;
277
278 /*
279 * Disable interrupts which might cause a timeout
280 * here. Remember that our exception vectors are
281 * at address 0 in the flash, and we don't want a
282 * (ticker) exception to happen while the flash
283 * chip is in programming mode.
284 */
285 cflag = icache_status ();
286 icache_disable ();
287 iflag = disable_interrupts ();
288
289 /* Disable interrupts which might cause a timeout here */
290/* flag = disable_interrupts (); */
291
292 /* Start erase on unprotected sectors */
293 for (sect = s_first; sect <= s_last; sect++) {
294 if (info->protect[sect] == 0) { /* not protected */
295 FPWV *addr = (FPWV *) (info->start[sect]);
296 FPW status;
297
298 printf ("Erasing sector %2d ... ", sect);
299
300 /* arm simple, non interrupt dependent timer */
301 reset_timer_masked ();
302
303 *addr = (FPW) INTEL_CLEAR; /* clear status register */
304 *addr = (FPW) INTEL_ERASE; /* erase setup */
305 *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
306
307 while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
308 if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
309 printf ("Timeout\n");
310 *addr = (FPW) INTEL_SUSPEND; /* suspend erase */
311 *addr = (FPW) INTEL_RESET; /* reset to read mode */
312 rcode = 1;
313 break;
314 }
315 }
316
317 *addr = INTEL_CLEAR; /* clear status register cmd. */
318 *addr = INTEL_RESET; /* resest to read mode */
319
320 printf (" done\n");
321 }
322 }
323
324 if (iflag)
325 enable_interrupts ();
326
327 if (cflag)
328 icache_enable ();
329
330 return rcode;
331}
332
333/*-----------------------------------------------------------------------
334 * Copy memory to flash, returns:
335 * 0 - OK
336 * 1 - write timeout
337 * 2 - Flash not erased
338 * 4 - Flash not identified
339 */
340
341int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
342{
343 ulong cp, wp;
344 FPW data;
345 int count, i, l, rc, port_width;
346
347 if (info->flash_id == FLASH_UNKNOWN) {
348 return 4;
349 }
350
351 /* get lower word aligned address */
352 wp = (addr & ~1);
353 port_width = 2;
354
355 /*
356 * handle unaligned start bytes
357 */
358 if ((l = addr - wp) != 0) {
359 data = 0;
360 for (i = 0, cp = wp; i < l; ++i, ++cp) {
361 data = (data << 8) | (*(uchar *) cp);
362 }
363 for (; i < port_width && cnt > 0; ++i) {
364 data = (data << 8) | *src++;
365 --cnt;
366 ++cp;
367 }
368 for (; cnt == 0 && i < port_width; ++i, ++cp) {
369 data = (data << 8) | (*(uchar *) cp);
370 }
371
372 if ((rc = write_data (info, wp, SWAP (data))) != 0) {
373 return (rc);
374 }
375 wp += port_width;
376 }
377
378 /*
379 * handle word aligned part
380 */
381 count = 0;
382 while (cnt >= port_width) {
383 data = 0;
384 for (i = 0; i < port_width; ++i) {
385 data = (data << 8) | *src++;
386 }
387 if ((rc = write_data (info, wp, SWAP (data))) != 0) {
388 return (rc);
389 }
390 wp += port_width;
391 cnt -= port_width;
392 if (count++ > 0x800) {
393 spin_wheel ();
394 count = 0;
395 }
396 }
397
398 if (cnt == 0) {
399 return (0);
400 }
401
402 /*
403 * handle unaligned tail bytes
404 */
405 data = 0;
406 for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
407 data = (data << 8) | *src++;
408 --cnt;
409 }
410 for (; i < port_width; ++i, ++cp) {
411 data = (data << 8) | (*(uchar *) cp);
412 }
413
414 return (write_data (info, wp, SWAP (data)));
415}
416
417/*-----------------------------------------------------------------------
418 * Write a word or halfword to Flash, returns:
419 * 0 - OK
420 * 1 - write timeout
421 * 2 - Flash not erased
422 */
423static int write_data (flash_info_t *info, ulong dest, FPW data)
424{
425 FPWV *addr = (FPWV *) dest;
426 ulong status;
427 int cflag, iflag;
428 int flag;
429
430 /* Check if Flash is (sufficiently) erased */
431 if ((*addr & data) != data) {
432 printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
433 return (2);
434 }
435 /*
436 * Disable interrupts which might cause a timeout
437 * here. Remember that our exception vectors are
438 * at address 0 in the flash, and we don't want a
439 * (ticker) exception to happen while the flash
440 * chip is in programming mode.
441 */
442 cflag = icache_status ();
443 icache_disable ();
444 iflag = disable_interrupts ();
445
446 /* Disable interrupts which might cause a timeout here */
447 /*flag = disable_interrupts (); */
448
449 *addr = (FPW) INTEL_PROG; /* write setup */
450 *addr = data;
451
452 /* arm simple, non interrupt dependent timer */
453 reset_timer_masked ();
454
455 /* wait while polling the status register */
456 while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
457 if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
458 *addr = (FPW) INTEL_RESET; /* restore read mode */
459 return (1);
460 }
461 }
462
463 *addr = (FPW) INTEL_RESET; /* restore read mode */
464
465 if (iflag)
466 enable_interrupts ();
467
468 if (cflag)
469 icache_enable ();
470
471 return (0);
472}
473
474void inline spin_wheel (void)
475{
476 static int p = 0;
477 static char w[] = "\\/-";
478
479 printf ("\010%c", w[p]);
480 (++p == 3) ? (p = 0) : 0;
481}
482
483/*-----------------------------------------------------------------------
484 * Set/Clear sector's lock bit, returns:
485 * 0 - OK
486 * 1 - Error (timeout, voltage problems, etc.)
487 */
488int flash_real_protect(flash_info_t *info, long sector, int prot)
489{
490 int i;
491 int rc = 0;
492 FPWV *addr = (FPWV *)(info->start[sector]);
493 int flag = disable_interrupts();
494
495 *addr = (FPW) INTEL_CLEAR; /* Clear status register */
496 if (prot) { /* Set sector lock bit */
497 *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */
498 *addr = (FPW) INTEL_PROTECT; /* set */
499 }
500 else { /* Clear sector lock bit */
501 *addr = (FPW) INTEL_LOCKBIT; /* All sectors lock bits */
502 *addr = (FPW) INTEL_CONFIRM; /* clear */
503 }
504
505 reset_timer_masked ();
506
507 while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
508 if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
509 printf("Flash lock bit operation timed out\n");
510 rc = 1;
511 break;
512 }
513 }
514
515 if (*addr != (FPW) INTEL_OK) {
516 printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
517 (uint)addr, (uint)*addr);
518 rc = 1;
519 }
520
521 if (!rc)
522 info->protect[sector] = prot;
523
524 /*
525 * Clear lock bit command clears all sectors lock bits, so
526 * we have to restore lock bits of protected sectors.
527 */
528 if (!prot)
529 {
530 for (i = 0; i < info->sector_count; i++)
531 {
532 if (info->protect[i])
533 {
534 reset_timer_masked ();
535 addr = (FPWV *) (info->start[i]);
536 *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */
537 *addr = (FPW) INTEL_PROTECT; /* set */
538 while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED)
539 {
540 if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
541 {
542 printf("Flash lock bit operation timed out\n");
543 rc = 1;
544 break;
545 }
546 }
547 }
548 }
549 }
550
551 if (flag)
552 enable_interrupts();
553
554 *addr = (FPW) INTEL_RESET; /* Reset to read array mode */
555
556 return rc;
557}