blob: 11d898527bf1fedc35667927d6938c95f0fab90a [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Andy Fleming61a21e92007-08-14 01:34:21 -05002 * Copyright 2004, 2007 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * Copyright(c) 2003 Motorola Inc.
wdenk42d1f032003-10-15 23:53:47 +00004 */
5
6#ifndef __MPC85xx_H__
7#define __MPC85xx_H__
8
Andy Fleming61a21e92007-08-14 01:34:21 -05009/* define for common ppc_asm.tmpl */
10#define EXC_OFF_SYS_RESET 0x100 /* System reset */
11#define _START_OFFSET 0
wdenk42d1f032003-10-15 23:53:47 +000012
13#if defined(CONFIG_E500)
14#include <e500.h>
15#endif
16
wdenk0ac6f8b2004-07-09 23:27:13 +000017/*
18 * SCCR - System Clock Control Register, 9-8
wdenk42d1f032003-10-15 23:53:47 +000019 */
wdenk0ac6f8b2004-07-09 23:27:13 +000020#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
21#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
wdenk42d1f032003-10-15 23:53:47 +000022#define SCCR_DFBRG_SHIFT 0
23
wdenk0ac6f8b2004-07-09 23:27:13 +000024#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
25#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
26#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
27#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
wdenk42d1f032003-10-15 23:53:47 +000028
Timur Tabie46fedf2011-08-04 18:03:41 -050029/*
30 * Define default values for some CCSR macros to make header files cleaner*
31 *
32 * To completely disable CCSR relocation in a board header file, define
33 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
34 * to a value that is the same as CONFIG_SYS_CCSRBAR.
35 */
36
37#ifdef CONFIG_SYS_CCSRBAR_PHYS
38#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
39CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
40#endif
41
42#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
43#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
44#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
45#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
46#endif
47
48#ifndef CONFIG_SYS_CCSRBAR
49#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
50#endif
51
52#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
53#ifdef CONFIG_PHYS_64BIT
54#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
55#else
56#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
57#endif
58#endif
59
60#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
61#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
62#endif
63
64#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
65 CONFIG_SYS_CCSRBAR_PHYS_LOW)
66
67#ifndef CONFIG_SYS_IMMR
68#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
69#endif
70
wdenk42d1f032003-10-15 23:53:47 +000071#endif /* __MPC85xx_H__ */