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Kristoffer Ericson80bf2bb2010-10-15 23:31:43 +02001/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 * 2004 (c) MontaVista Software, Inc.
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Kristoffer Ericson80bf2bb2010-10-15 23:31:43 +02009 */
10
11
12#include "config.h"
13#include "version.h"
14
15
16/*-----------------------------------------------------------------------
17 * Board defines:
18 */
19
20#define MDCNFG 0x00
21#define MDCAS00 0x04
22#define MDCAS01 0x08
23#define MDCAS02 0x0C
24#define MSC0 0x10
25#define MSC1 0x14
26#define MECR 0x18
27#define MDREFR 0x1C
28#define MDCAS20 0x20
29#define MDCAS21 0x24
30#define MDCAS22 0x28
31#define MSC2 0x2C
32#define SMCNFG 0x30
33
34#define GPDR 0x04
35#define GPSR 0x08
36#define GPCR 0x0C
37#define GAFR 0x1C
38
39#define PPDR 0x00
40#define PPSR 0x04
41#define PPAR 0x08
42
43#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
44#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
45#define MDREFR_K0DB2 (1 << 18)
46#define MDREFR_K1DB2 (1 << 22)
47#define MDREFR_K2DB2 (1 << 26)
48
49#define MDREFR_K0RUN (1 << 17)
50#define MDREFR_K1RUN (1 << 21)
51#define MDREFR_K2RUN (1 << 25)
52
53#define MDREFR_SLFRSH (1 << 31)
54#define MDREFR_E1PIN (1 << 20)
55
56#define PSSR 0x04
57#define PSSR_DH 0x00000008
58#define POSR 0x08
59#define RCSR 0x04
60
61/*-----------------------------------------------------------------------
62 * Setup parameters for the board:
63 */
64MEM_BASE: .long 0xa0000000
65MEM_START: .long 0xc0000000
66PWR_BASE: .word 0x90020000
67RST_BASE: .long 0x90030000
68PPC_BASE: .long 0x90060000
69GPIO_BASE: .long 0x90040000
70IC_BASE: .word 0x90050000
71
72cpuspeed: .word 0xa0
73/* calculated from old blob bootloader */
74mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
75mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
76mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
77mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
78msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
79msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
80mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
81mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
82mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
83mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
84mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
85msc2: .long 0x201d2959 /* msc2 0x201d2959 */
86smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
87
88pin_set_out: .long 0x37ff70
89pin_set_dir: .long 0x11480
90
91gpdr_set: .long 0x0B3A0900
92gpsr_set: .long 0x02100800
93gpcr_set: .long 0x092A0100
94gafr_set: .long 0x08600000
95
96.globl lowlevel_init
97lowlevel_init:
98
Kristoffer Ericsonf4f88922010-11-06 14:24:27 +010099
100 /* this is required for flashing */
101 ldr r0, PPC_BASE
102 ldr r1, pin_set_out
103 str r1, [r0, #PPSR]
104 ldr r1, pin_set_dir
105 str r1, [r0, #PPDR]
Kristoffer Ericson80bf2bb2010-10-15 23:31:43 +0200106
107 /* Setting up the memory and stuff */
108 /***********************************/
109
110 ldr r0, MEM_BASE
111
112 ldr r1, mdcnfg
113 str r1, [r0, #MDCNFG]
114 ldr r1, mdcas00
115 str r1, [r0, #MDCAS00]
116 ldr r1, mdcas01
117 str r1, [r0, #MDCAS01]
118 ldr r1, mdcas02
119 str r1, [r0, #MDCAS02]
120 ldr r1, mdcas20
121 str r1, [r0, #MDCAS20]
122 ldr r1, mdcas21
123 str r1, [r0, #MDCAS21]
124 ldr r1, mdcas22
125 str r1, [r0, #MDCAS22]
126
127 /* clear kxDB2 */
128 ldr r2, [r0, #MDREFR]
129 bic r2, r2, #MDREFR_K0DB2
130 bic r2, r2, #MDREFR_K1DB2
131 bic r2, r2, #MDREFR_K2DB2
132 str r2, [r0, #MDREFR]
133
134 ldr r2, [r0, #MDREFR]
135 orr r2, r2, #MDREFR_TRASR(7)
136
137 mov r4, #0x2000
138 spin: subs r4, r4, #1
139 bne spin
140
141 ldr r1, PWR_BASE
142 mov r2, #PSSR_DH
143 str r2, [r1, #PSSR]
144
145 ldr r2, [r0, #MDREFR]
146 bic r2, r2, #MDREFR_K0DB2
147 bic r2, r2, #MDREFR_K1DB2
148 bic r2, r2, #MDREFR_K2DB2
149 str r2, [r0, #MDREFR]
150
151 ldr r2, [r0, #MDREFR]
152 orr r2, r2, #MDREFR_TRASR(7)
153 orr r2, r2, #MDREFR_DRI(12)
154 orr r2, r2, #MDREFR_K0DB2
155 orr r2, r2, #MDREFR_K1DB2
156 orr r2, r2, #MDREFR_K2DB2
157 str r2, [r0, #MDREFR]
158
159 ldr r2, [r0, #MDREFR]
160 orr r2, r2, #MDREFR_K0RUN
161 orr r2, r2, #MDREFR_K1RUN
162 orr r2, r2, #MDREFR_K2RUN
163 str r2, [r0, #MDREFR]
164
165 ldr r2, [r0, #MDREFR]
166 bic r2, r2, #MDREFR_SLFRSH
167 str r2, [r0, #MDREFR]
168
169 ldr r2, [r0, #MDREFR]
170 orr r2, r2, #MDREFR_E1PIN
171 str r2, [r0, #MDREFR]
172
173 ldr r2, MEM_START
174.rept 8
175 ldr r3, [r2]
176.endr
177
Kristoffer Ericsonf4f88922010-11-06 14:24:27 +0100178 ldr r2, [r0, #MDCNFG]
179 orr r2, r2, #0x00000003
180 orr r2, r2, #0x00030000
181 str r2, [r0, #MDCNFG]
182
Kristoffer Ericson80bf2bb2010-10-15 23:31:43 +0200183 ldr r1, msc0
184 str r1, [r0, #MSC0]
185 ldr r1, msc1
186 str r1, [r0, #MSC1]
187 ldr r1, msc2
188 str r1, [r0, #MSC2]
189 ldr r1, smcnfg
190 str r1, [r0, #SMCNFG]
Kristoffer Ericson80bf2bb2010-10-15 23:31:43 +0200191 ldr r1, mecr
192 str r1, [r0, #MECR]
193
Kristoffer Ericson80bf2bb2010-10-15 23:31:43 +0200194 mov pc, lr