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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkbfc81252006-03-06 13:03:37 +010015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
stroesea20b27a2004-12-16 18:05:42 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/*************************************************************************
29 * (c) 2004 esd gmbh Hannover
30 *
31 *
32 * from db64360.h file
33 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
34 *
35 ************************************************************************/
36
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
stroesea20b27a2004-12-16 18:05:42 +000041/* This define must be before the core.h include */
42#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
43
44#ifndef __ASSEMBLY__
45#include <../board/Marvell/include/core.h>
46#endif
47/*-----------------------------------------------------*/
48
49#include "../board/esd/cpci750/local.h"
50
51/*
52 * High Level Configuration Options
53 * (easy to change)
54 */
55
56#define CONFIG_750FX /* we have a 750FX (override local.h) */
57
58#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
59
Wolfgang Denkbfc81252006-03-06 13:03:37 +010060#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
stroesea20b27a2004-12-16 18:05:42 +000061
Reinhard Arlt0738e242010-04-13 09:59:09 +020062#define CONFIG_MV64360_ECC /* enable ECC support */
stroesea20b27a2004-12-16 18:05:42 +000063
Becky Bruce31d82672008-05-08 19:02:12 -050064#define CONFIG_HIGH_BATS 1 /* High BATs supported */
65
stroesea20b27a2004-12-16 18:05:42 +000066/* which initialization functions to call for this board */
67#define CONFIG_MISC_INIT_R
68#define CONFIG_BOARD_PRE_INIT
69#define CONFIG_BOARD_EARLY_INIT_F 1
70
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_BOARD_NAME "CPCI750"
stroesea20b27a2004-12-16 18:05:42 +000072#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074/*#define CONFIG_SYS_HUSH_PARSER*/
75#define CONFIG_SYS_HUSH_PARSER
stroesea20b27a2004-12-16 18:05:42 +000076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroesea20b27a2004-12-16 18:05:42 +000078
Stefan Roese0a14d6b2009-06-04 13:35:35 +020079#define CONFIG_CMDLINE_EDITING /* add command line history */
80#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Stefan Roesea7b9fb92006-01-18 20:05:34 +010081
stroesea20b27a2004-12-16 18:05:42 +000082/* Define which ETH port will be used for connecting the network */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_ETH_PORT ETH_0
stroesea20b27a2004-12-16 18:05:42 +000084
85/*
86 * The following defines let you select what serial you want to use
87 * for your console driver.
88 *
89 * what to do:
Wolfgang Denkbfc81252006-03-06 13:03:37 +010090 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
stroesea20b27a2004-12-16 18:05:42 +000092 * to 0 below.
93 *
94 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
95 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
96 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +010097#define CONFIG_MPSC
stroesea20b27a2004-12-16 18:05:42 +000098#define CONFIG_MPSC_PORT 0
99
100/* to change the default ethernet port, use this define (options: 0, 1, 2) */
101#define CONFIG_NET_MULTI
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100102#define MV_ETH_DEVS 1
stroesea20b27a2004-12-16 18:05:42 +0000103#define CONFIG_ETHER_PORT 0
104
105#undef CONFIG_ETHER_PORT_MII /* use RMII */
106
107#define CONFIG_BOOTDELAY 5 /* autoboot disabled */
108
109#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
110
111#define CONFIG_ZERO_BOOTDELAY_CHECK
112
113
114#undef CONFIG_BOOTARGS
115
116/* -----------------------------------------------------------------------------
117 * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
118 */
119
120#define CONFIG_IPADDR "192.168.0.185"
121
122#define CONFIG_SERIAL "AA000001"
123#define CONFIG_SERVERIP "10.0.0.79"
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100124#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
stroesea20b27a2004-12-16 18:05:42 +0000125
126#define CONFIG_TESTDRAMDATA y
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100127#define CONFIG_TESTDRAMADDRESS n
stroesea20b27a2004-12-16 18:05:42 +0000128#define CONFIG_TESETDRAMWALK n
129
130/* ----------------------------------------------------------------------------- */
131
132
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100133#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
stroesea20b27a2004-12-16 18:05:42 +0000135
136#undef CONFIG_WATCHDOG /* watchdog disabled */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100137#undef CONFIG_ALTIVEC /* undef to disable */
stroesea20b27a2004-12-16 18:05:42 +0000138
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500139/*
140 * BOOTP options
141 */
142#define CONFIG_BOOTP_SUBNETMASK
143#define CONFIG_BOOTP_GATEWAY
144#define CONFIG_BOOTP_HOSTNAME
145#define CONFIG_BOOTP_BOOTPATH
146#define CONFIG_BOOTP_BOOTFILESIZE
stroesea20b27a2004-12-16 18:05:42 +0000147
148
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500149/*
150 * Command line configuration.
151 */
152#include <config_cmd_default.h>
153
Wolfgang Denk5728be32007-08-06 01:01:49 +0200154#define CONFIG_CMD_ASKENV
155#define CONFIG_CMD_I2C
156#define CONFIG_CMD_CACHE
157#define CONFIG_CMD_EEPROM
158#define CONFIG_CMD_PCI
159#define CONFIG_CMD_ELF
160#define CONFIG_CMD_DATE
161#define CONFIG_CMD_NET
162#define CONFIG_CMD_PING
163#define CONFIG_CMD_IDE
164#define CONFIG_CMD_FAT
165#define CONFIG_CMD_EXT2
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500166
stroesea20b27a2004-12-16 18:05:42 +0000167
168#define CONFIG_DOS_PARTITION
169
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100170#define CONFIG_USE_CPCIDVI
171
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100172#ifdef CONFIG_USE_CPCIDVI
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100173#define CONFIG_VIDEO
174#define CONFIG_VIDEO_CT69000
175#define CONFIG_CFB_CONSOLE
176#define CONFIG_VIDEO_SW_CURSOR
177#define CONFIG_VIDEO_LOGO
178#define CONFIG_I8042_KBD
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_ISA_IO 0
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100180#endif
181
stroesea20b27a2004-12-16 18:05:42 +0000182/*
183 * Miscellaneous configurable options
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
186#define CONFIG_SYS_I2C_MULTI_EEPROMS
187#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */
stroesea20b27a2004-12-16 18:05:42 +0000188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
190#define CONFIG_SYS_LONGHELP /* undef to save memory */
191#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500192#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000194#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000196#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
198#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
199#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201/*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */
202/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
203/*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000204
205/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_DRAM_TEST
stroesea20b27a2004-12-16 18:05:42 +0000207 * DRAM tests
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208 * CONFIG_SYS_DRAM_TEST - enables the following tests.
stroesea20b27a2004-12-16 18:05:42 +0000209 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100211 * Environment variable 'test_dram_data' must be
212 * set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100214 * addressable. Environment variable
215 * 'test_dram_address' must be set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100217 * This test takes about 6 minutes to test 64 MB.
218 * Environment variable 'test_dram_walk' must be
219 * set to 'y'.
stroesea20b27a2004-12-16 18:05:42 +0000220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_DRAM_TEST
222#if defined(CONFIG_SYS_DRAM_TEST)
223#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
224/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
225#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
226#define CONFIG_SYS_DRAM_TEST_DATA
227#define CONFIG_SYS_DRAM_TEST_ADDRESS
228#define CONFIG_SYS_DRAM_TEST_WALK
229#endif /* CONFIG_SYS_DRAM_TEST */
stroesea20b27a2004-12-16 18:05:42 +0000230
231#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
stroesea20b27a2004-12-16 18:05:42 +0000233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
stroesea20b27a2004-12-16 18:05:42 +0000235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200237#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
stroesea20b27a2004-12-16 18:05:42 +0000238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
stroesea20b27a2004-12-16 18:05:42 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_TCLK 133000000
stroesea20b27a2004-12-16 18:05:42 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243/*#define CONFIG_SYS_750FX_HID0 0x8000c084*/
244#define CONFIG_SYS_750FX_HID0 0x80008484
245#define CONFIG_SYS_750FX_HID1 0x54800000
246#define CONFIG_SYS_750FX_HID2 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000247
248/*
249 * Low Level Configuration Settings
250 * (address mappings, register initial values, etc.)
251 * You should know what you are doing if you make changes here.
252 */
253
254/*-----------------------------------------------------------------------
255 * Definitions for initial stack pointer and data area
256 */
257
258 /*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
stroesea20b27a2004-12-16 18:05:42 +0000260 * To an unused memory region. The stack will remain in cache until RAM
261 * is initialized
262*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#undef CONFIG_SYS_INIT_RAM_LOCK
264/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
265/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
266#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
267#define CONFIG_SYS_INIT_RAM_END 0x1000
268#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
269#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
stroesea20b27a2004-12-16 18:05:42 +0000270
271#define RELOCATE_INTERNAL_RAM_ADDR
272#ifdef RELOCATE_INTERNAL_RAM_ADDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
274#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000
stroesea20b27a2004-12-16 18:05:42 +0000275#endif
276
277/*-----------------------------------------------------------------------
278 * Start addresses for the final memory configuration
279 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_SDRAM_BASE 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000283/* Dummies for BAT 4-7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
285#define CONFIG_SYS_SDRAM2_BASE 0x20000000
286#define CONFIG_SYS_SDRAM3_BASE 0x30000000
287#define CONFIG_SYS_SDRAM4_BASE 0x40000000
288#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
289#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
290#define CONFIG_SYS_MONITOR_BASE 0xfff00000
291#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
stroesea20b27a2004-12-16 18:05:42 +0000292
293/*-----------------------------------------------------------------------
294 * FLASH related
295 *----------------------------------------------------------------------*/
296
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200297#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
299#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
300#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
301#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */
302#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
303#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */
304#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
305#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
306 CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \
307 CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \
308 CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
309#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
stroesea20b27a2004-12-16 18:05:42 +0000310
311/* areas to map different things with the GT in physical space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_DRAM_BANKS 4
stroesea20b27a2004-12-16 18:05:42 +0000313
314/* What to put in the bats. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
stroesea20b27a2004-12-16 18:05:42 +0000316
317/* Peripheral Device section */
318
319/*******************************************************/
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100320/* We have on the cpci750 Board : */
321/* GT-Chipset Register Area */
322/* GT-Chipset internal SRAM 256k */
323/* SRAM on external device module */
324/* Real time clock on external device module */
325/* dobble UART on external device module */
326/* Data flash on external device module */
327/* Boot flash on external device module */
stroesea20b27a2004-12-16 18:05:42 +0000328/*******************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
330#define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
stroesea20b27a2004-12-16 18:05:42 +0000331
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100332#undef MARVEL_STANDARD_CFG
333#ifndef MARVEL_STANDARD_CFG
stroesea20b27a2004-12-16 18:05:42 +0000334/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
336/*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
337#define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */
stroesea20b27a2004-12-16 18:05:42 +0000338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */
340#define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */
341#define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */
342#define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
343#define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
stroesea20b27a2004-12-16 18:05:42 +0000344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */
346#define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */
347#define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */
348#define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */
349#define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */
stroesea20b27a2004-12-16 18:05:42 +0000350
351/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
352#endif
353
354/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
356#define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
357#define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
358#define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */
359#define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
stroesea20b27a2004-12-16 18:05:42 +0000360
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100361 /* c 4 a 8 2 4 1 c */
362 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
wdenkefe2a4d2004-12-16 21:44:03 +0000363 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
364 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
365 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
stroesea20b27a2004-12-16 18:05:42 +0000366
367
368/* MPP Control MV64360 Appendix P P. 632*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */
370#define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */
371#define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */
372#define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */
373/* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */
stroesea20b27a2004-12-16 18:05:42 +0000374
375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
stroesea20b27a2004-12-16 18:05:42 +0000377
378/* setup new config_value for MV64360 DDR-RAM To_do !! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */
380/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */
stroesea20b27a2004-12-16 18:05:42 +0000381 /* GB has high prio.
382 idma has low prio
383 MPSC has low prio
384 pci has low prio 1 and 2
385 cpu has high prio
386 Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
387 ECC disable
388 non registered DRAM */
389 /* 31:26 25:22 21:20 19 18 17 16 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100390 /* 100001 0000 010 0 0 0 0 */
stroesea20b27a2004-12-16 18:05:42 +0000391 /* refresh_count=0x400
392 phisical interleaving disable
393 virtual interleaving enable */
394 /* 15 14 13:0 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100395 /* 0 1 0x400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
stroesea20b27a2004-12-16 18:05:42 +0000397
398
399/*-----------------------------------------------------------------------
400 * PCI stuff
401 *-----------------------------------------------------------------------
402 */
403
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100404#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
405#define PCI_HOST_FORCE 1 /* configure as pci host */
406#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroesea20b27a2004-12-16 18:05:42 +0000407
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100408#define CONFIG_PCI /* include pci support */
409#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
410#define CONFIG_PCI_PNP /* do pci plug-and-play */
411#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
stroesea20b27a2004-12-16 18:05:42 +0000412
413/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
415#define CONFIG_SYS_PCI0_MEM_SIZE _128M
416#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
417#define CONFIG_SYS_PCI1_MEM_SIZE _128M
stroesea20b27a2004-12-16 18:05:42 +0000418
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
420#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
stroesea20b27a2004-12-16 18:05:42 +0000421
stroesea20b27a2004-12-16 18:05:42 +0000422/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
424#define CONFIG_SYS_PCI0_IO_SIZE _16M
425#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
426#define CONFIG_SYS_PCI1_IO_SIZE _16M
stroesea20b27a2004-12-16 18:05:42 +0000427
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
429#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
430#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
431#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100434
stroesea20b27a2004-12-16 18:05:42 +0000435#if defined (CONFIG_750CX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_PCI_IDSEL 0x0
stroesea20b27a2004-12-16 18:05:42 +0000437#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_PCI_IDSEL 0x30
stroesea20b27a2004-12-16 18:05:42 +0000439#endif
440
441/*-----------------------------------------------------------------------
442 * IDE/ATA stuff
443 *-----------------------------------------------------------------------
444 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100445#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
446#undef CONFIG_IDE_LED /* no led for ide supported */
447#define CONFIG_IDE_RESET /* no reset for ide supported */
448#define CONFIG_IDE_PREINIT /* check for units */
stroesea20b27a2004-12-16 18:05:42 +0000449
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */
451#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
stroesea20b27a2004-12-16 18:05:42 +0000452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_ATA_BASE_ADDR 0
454#define CONFIG_SYS_ATA_IDE0_OFFSET 0
455#define CONFIG_SYS_ATA_IDE1_OFFSET 0
stroesea20b27a2004-12-16 18:05:42 +0000456
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
458#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
459#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea20b27a2004-12-16 18:05:42 +0000460
461
462/*----------------------------------------------------------------------
463 * Initial BAT mappings
464 */
465
466/* NOTES:
467 * 1) GUARDED and WRITE_THRU not allowed in IBATS
468 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
469 */
470
471/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
473#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
474#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
475#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
stroesea20b27a2004-12-16 18:05:42 +0000476
477/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
479#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
480#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
481#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
stroesea20b27a2004-12-16 18:05:42 +0000482
483/* PCI0, PCI1 in one BAT */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
485#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
486#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
487#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
stroesea20b27a2004-12-16 18:05:42 +0000488
489/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
491#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
492#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
493#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
stroesea20b27a2004-12-16 18:05:42 +0000494
495/*
496 * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
497 * IBAT4 and DBAT4
498 * FIXME: ingo disable BATs for Linux Kernel
499 */
500#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */
501/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */
502
503#ifdef SETUP_HIGH_BATS_FX750
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
505#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
506#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
507#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000508
509/* IBAT5 and DBAT5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
511#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
512#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
513#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
stroesea20b27a2004-12-16 18:05:42 +0000514
515/* IBAT6 and DBAT6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
517#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
518#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
519#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
stroesea20b27a2004-12-16 18:05:42 +0000520
521/* IBAT7 and DBAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
523#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
524#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
525#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
stroesea20b27a2004-12-16 18:05:42 +0000526
527#else /* set em out of range for Linux !!!!!!!!!!! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
529#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
530#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
531#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000532
533/* IBAT5 and DBAT5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
535#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
536#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
537#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000538
539/* IBAT6 and DBAT6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
541#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
542#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
543#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000544
545/* IBAT7 and DBAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
547#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
548#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
549#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000550
551#endif
552/* FIXME: ingo end: disable BATs for Linux Kernel */
553
554/* I2C addresses for the two DIMM SPD chips */
555#define DIMM0_I2C_ADDR 0x51
556#define DIMM1_I2C_ADDR 0x52
557
558/*
559 * For booting Linux, the board info and command line data
560 * have to be in the first 8 MB of memory, since this is
561 * the maximum mapped by the Linux kernel during initialization.
562 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000564
565/*-----------------------------------------------------------------------
566 * FLASH organization
567 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
stroesea20b27a2004-12-16 18:05:42 +0000569
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
571#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
572#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000573
574#if 0
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200575#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200576#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
577#define CONFIG_ENV_SECT_SIZE 0x10000
578#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
stroesea20b27a2004-12-16 18:05:42 +0000580#endif
581
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200582#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
584#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
585#define CONFIG_SYS_I2C_EEPROM_ADDR 0x050
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200586#define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
587#define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000588
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
590#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
591#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
stroesea20b27a2004-12-16 18:05:42 +0000592
593/*-----------------------------------------------------------------------
594 * Cache Configuration
595 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500597#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200598#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
stroesea20b27a2004-12-16 18:05:42 +0000599#endif
600
601/*-----------------------------------------------------------------------
602 * L2CR setup -- make sure this is right for your board!
603 * look in include/mpc74xx.h for the defines used here
604 */
605
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200606/*#define CONFIG_SYS_L2*/
607#undef CONFIG_SYS_L2
stroesea20b27a2004-12-16 18:05:42 +0000608
609/* #ifdef CONFIG_750CX*/
610#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
611#define L2_INIT 0
612#else
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100613#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
stroesea20b27a2004-12-16 18:05:42 +0000614 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
615#endif
616
617#define L2_ENABLE (L2_INIT | L2CR_L2E)
618
619/*
620 * Internal Definitions
621 *
622 * Boot Flags
623 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100624#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
stroesea20b27a2004-12-16 18:05:42 +0000625#define BOOTFLAG_WARM 0x02 /* Software reboot */
626
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200627#define CONFIG_SYS_BOARD_ASM_INIT 1
stroesea20b27a2004-12-16 18:05:42 +0000628
Stefan Roese58f10462009-06-04 13:35:39 +0200629#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
Reinhard Arlt0738e242010-04-13 09:59:09 +0200630#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0)
631#define CONFIG_SYS_PLD_VER 0xf0e00000
Stefan Roese58f10462009-06-04 13:35:39 +0200632
stroesea20b27a2004-12-16 18:05:42 +0000633#endif /* __CONFIG_H */