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Matthias Fuchs99d8b232009-07-22 13:56:21 +02001/*
2 * (C) Copyright 2009
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_405EP 1 /* This is a PPC405 CPU */
28#define CONFIG_4xx 1 /* ...member of PPC4xx family */
29#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
30
31#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
32#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
33#define CONFIG_BOARD_TYPES 1 /* support board types */
34
35#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
36
37#define CONFIG_BAUDRATE 115200
38#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
39
40#undef CONFIG_BOOTARGS
41#undef CONFIG_BOOTCOMMAND
42
43#define CONFIG_PREBOOT /* enable preboot variable */
44
45#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
46
47#define CONFIG_NET_MULTI 1
48#define CONFIG_HAS_ETH1
49
50#define CONFIG_PPC4xx_EMAC
51#define CONFIG_MII 1 /* MII PHY management */
52#define CONFIG_PHY_ADDR 1 /* PHY address */
53#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
54
55#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
56
57/*
58 * BOOTP options
59 */
60#define CONFIG_BOOTP_SUBNETMASK
61#define CONFIG_BOOTP_GATEWAY
62#define CONFIG_BOOTP_HOSTNAME
63#define CONFIG_BOOTP_BOOTPATH
64#define CONFIG_BOOTP_DNS
65#define CONFIG_BOOTP_DNS2
66#define CONFIG_BOOTP_SEND_HOSTNAME
67
68/*
69 * Command line configuration.
70 */
71#include <config_cmd_default.h>
72
73#define CONFIG_CMD_BSP
74#define CONFIG_CMD_CHIP_CONFIG
75#define CONFIG_CMD_DATE
76#define CONFIG_CMD_DHCP
77#define CONFIG_CMD_EEPROM
78#define CONFIG_CMD_ELF
79#define CONFIG_CMD_I2C
80#define CONFIG_CMD_IRQ
81#define CONFIG_CMD_MII
82#define CONFIG_CMD_NFS
83#define CONFIG_CMD_PCI
84#define CONFIG_CMD_PING
85
86#define CONFIG_OF_LIBFDT
87#define CONFIG_OF_BOARD_SETUP
88
89#undef CONFIG_WATCHDOG /* watchdog disabled */
90#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
91#define CONFIG_PRAM 0
92
93/*
94 * Miscellaneous configurable options
95 */
96#define CONFIG_SYS_LONGHELP
97#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
98
99#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
100#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
101#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
102#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
103
104#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
105#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
106
107#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
108#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
109
110#undef CONFIG_SYS_EXT_SERIAL_CLOCK
111#define CONFIG_SYS_BASE_BAUD 691200
112#define CONFIG_UART1_CONSOLE
113
114/* The following table includes the supported baudrates */
115#define CONFIG_SYS_BAUDRATE_TABLE \
116 { 9600, 19200, 38400, 57600, 115200 }
117
118#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
119#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
120
121#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
122
123#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
124#define CONFIG_LOOPW 1 /* enable loopw command */
125#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
126#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
127#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
128
129#define CONFIG_AUTOBOOT_KEYED 1
130#define CONFIG_AUTOBOOT_PROMPT \
131 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
132#undef CONFIG_AUTOBOOT_DELAY_STR
133#define CONFIG_AUTOBOOT_STOP_STR " "
134
135/*
136 * PCI stuff
137 */
138#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
139#define PCI_HOST_FORCE 1 /* configure as pci host */
140#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
141
142#define CONFIG_PCI /* include pci support */
143#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
144#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
145
146#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
147
148/*
149 * PCI identification
150 */
151#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
152#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
153#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
154#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
155#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
156
157#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
158#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
159
160#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
161#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
162#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
163#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
164#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
165#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
166
Matthias Fuchs82379b52009-09-07 17:00:41 +0200167#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
168
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200169/*
170 * For booting Linux, the board info and command line data
171 * have to be in the first 8 MB of memory, since this is
172 * the maximum mapped by the Linux kernel during initialization.
173 */
174#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
175/*
176 * FLASH organization
177 */
178#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
179#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
180
181#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
182
183#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
184#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
185
186#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
187#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
188
189#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
190#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
191
192#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
193#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
194
195
196/*
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
199 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
200 */
201#define CONFIG_SYS_SDRAM_BASE 0x00000000
202#define CONFIG_SYS_FLASH_BASE 0xfe000000
203#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
204#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
205#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
206
207/*
208 * Environment in EEPROM setup
209 */
210#define CONFIG_ENV_IS_IN_EEPROM 1
211#define CONFIG_ENV_OFFSET 0x100
212#define CONFIG_ENV_SIZE 0x700
213
214/*
215 * I2C EEPROM (24W16) for environment
216 */
217#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200218#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200219#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
220#define CONFIG_SYS_I2C_SLAVE 0x7F
221
222#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
223#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
224/* mask of address bits that overflow into the "EEPROM chip address" */
225#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
226#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
227 /* 16 byte page write mode using*/
228 /* last 4 bits of the address */
229#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
230#define CONFIG_SYS_EEPROM_WREN 1
231
232#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
233#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
234#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
235
236/*
237 * RTC
238 */
239#define CONFIG_RTC_RX8025
240
241/*
242 * External Bus Controller (EBC) Setup
243 * (max. 55MHZ EBC clock)
244 */
245/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
246#define CONFIG_SYS_EBC_PB0AP 0x03017200
247#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
248
249/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
250#define CONFIG_SYS_CPLD_BASE 0xef000000
251#define CONFIG_SYS_EBC_PB1AP 0x00800000
252#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
253
254/*
255 * Definitions for initial stack pointer and data area (in data cache)
256 */
257/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
258#define CONFIG_SYS_TEMP_STACK_OCM 1
259
260/* On Chip Memory location */
261#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
262#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
263/* inside SDRAM */
264#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
265/* End of used area in RAM */
266#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
267
268#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */
269#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
270 CONFIG_SYS_GBL_DATA_SIZE)
271#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
272
273/*
274 * GPIO Configuration
275 */
276#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
277{ \
278/* GPIO Core 0 */ \
279{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
280{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
281{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
282{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
283{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
284{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
285{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
286{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
287{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
288{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
289{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
290{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
291{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
292{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
293{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
294{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
295{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
296{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
297{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
298{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
299{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
300{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
301{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
302{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
303{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
304{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
305{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
306{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
307{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
308{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
309{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
310{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
311} \
312}
313
314#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
315#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
316#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
317#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
318#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
319#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
320#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
321#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
322#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
323#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
324
325/*
326 * Default speed selection (cpu_plb_opb_ebc) in mhz.
327 * This value will be set if iic boot eprom is disabled.
328 */
329#undef CONFIG_SYS_FCPU333MHZ
330#define CONFIG_SYS_FCPU266MHZ
331#undef CONFIG_SYS_FCPU133MHZ
332
333#if defined(CONFIG_SYS_FCPU333MHZ)
334/*
335 * CPU: 333MHz
336 * PLB/SDRAM/MAL: 111MHz
337 * OPB: 55MHz
338 * EBC: 55MHz
339 * PCI: 55MHz (111MHz on M66EN=1)
340 */
341#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
342 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
343 PLL_MALDIV_1 | PLL_PCIDIV_2)
344#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
345 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
346 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
347#endif
348
349#if defined(CONFIG_SYS_FCPU266MHZ)
350/*
351 * CPU: 266MHz
352 * PLB/SDRAM/MAL: 133MHz
353 * OPB: 66MHz
354 * EBC: 44MHz
355 * PCI: 44MHz (66MHz on M66EN=1)
356 */
357#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
358 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
359 PLL_MALDIV_1 | PLL_PCIDIV_3)
360#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
361 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
362 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
363#endif
364
365#if defined(CONFIG_SYS_FCPU133MHZ)
366/*
367 * CPU: 133MHz
368 * PLB/SDRAM/MAL: 133MHz
369 * OPB: 66MHz
370 * EBC: 44MHz
371 * PCI: 44MHz (66MHz on M66EN=1)
372 */
373#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
374 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
375 PLL_MALDIV_1 | PLL_PCIDIV_3)
376#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
377 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
378 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
379#endif
380
381#endif /* __CONFIG_H */