blob: 37011c0935c4b0ba6c2b605e34ef8df018ad13ef [file] [log] [blame]
David Brownell28b00322009-05-15 23:48:37 +02001/*
2 * Copyright (C) 2009 David Brownell
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
David Brownell28b00322009-05-15 23:48:37 +020022
23/* Spectrum Digital TMS320DM355 EVM board */
24#define DAVINCI_DM355EVM
25
26#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
27#define CONFIG_SKIP_RELOCATE_UBOOT
28#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
29#define CONFIG_SYS_CONSOLE_INFO_QUIET
30#define CONFIG_DISPLAY_CPUINFO
31
32/* SoC Configuration */
33#define CONFIG_ARM926EJS /* arm926ejs CPU */
34#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
35#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
36#define CONFIG_SYS_HZ 1000
37#define CONFIG_SOC_DM355
38
39/* Memory Info */
40#define CONFIG_NR_DRAM_BANKS 1
41#define PHYS_SDRAM_1 0x80000000
Sandeep Paulraja16df2c2009-09-08 17:09:52 -040042#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
David Brownell28b00322009-05-15 23:48:37 +020043
44/* Serial Driver info: UART0 for console */
45#define CONFIG_SYS_NS16550
46#define CONFIG_SYS_NS16550_SERIAL
47#define CONFIG_SYS_NS16550_REG_SIZE -4
48#define CONFIG_SYS_NS16550_COM1 0x01c20000
49#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
50#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
51#define CONFIG_CONS_INDEX 1
52#define CONFIG_BAUDRATE 115200
53
54/* Ethernet: external DM9000 */
55#define CONFIG_DRIVER_DM9000 1
56#define CONFIG_DM9000_BASE 0x04014000
57#define DM9000_IO CONFIG_DM9000_BASE
58#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
Jean-Christophe PLAGNIOL-VILLARDc8badbe2009-06-28 14:14:21 +020059#define CONFIG_NET_MULTI
David Brownell28b00322009-05-15 23:48:37 +020060
61/* I2C */
62#define CONFIG_HARD_I2C
63#define CONFIG_DRIVER_DAVINCI_I2C
64#define CONFIG_SYS_I2C_SPEED 400000
65#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
66
67/* NAND: socketed, two chipselects, normally 2 GBytes */
Sandeep Paulraj409ec372009-09-08 18:08:06 -040068#define CONFIG_NAND_DAVINCI
Nick Thompson97f4eb82009-12-12 12:12:26 -050069#define CONFIG_SYS_NAND_CS 2
David Brownell28b00322009-05-15 23:48:37 +020070#define CONFIG_SYS_NAND_USE_FLASH_BBT
Sandeep Paulraj409ec372009-09-08 18:08:06 -040071#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
72#define CONFIG_SYS_NAND_PAGE_2K
David Brownell28b00322009-05-15 23:48:37 +020073
74#define CONFIG_SYS_NAND_LARGEPAGE
75#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
76/* socket has two chipselects, nCE0 gated by address BIT(14) */
77#define CONFIG_SYS_MAX_NAND_DEVICE 1
78#define CONFIG_SYS_NAND_MAX_CHIPS 2
79
80/* USB: OTG connector */
81/* NYET -- #define CONFIG_USB_DAVINCI */
82
83/* U-Boot command configuration */
84#include <config_cmd_default.h>
85
86#undef CONFIG_CMD_BDI
87#undef CONFIG_CMD_FLASH
88#undef CONFIG_CMD_FPGA
89#undef CONFIG_CMD_SETGETDCR
90
91#define CONFIG_CMD_ASKENV
92#define CONFIG_CMD_DHCP
93#define CONFIG_CMD_I2C
94#define CONFIG_CMD_PING
95#define CONFIG_CMD_SAVES
96
97#ifdef CONFIG_NAND_DAVINCI
98#define CONFIG_CMD_MTDPARTS
99#define CONFIG_MTD_PARTITIONS
Sandeep Paulraj409ec372009-09-08 18:08:06 -0400100#define CONFIG_MTD_DEVICE
David Brownell28b00322009-05-15 23:48:37 +0200101#define CONFIG_CMD_NAND
102#define CONFIG_CMD_UBI
103#define CONFIG_RBTREE
104#endif
105
David Brownell28b00322009-05-15 23:48:37 +0200106#ifdef CONFIG_USB_DAVINCI
107#define CONFIG_MUSB_HCD
108#define CONFIG_CMD_USB
109#define CONFIG_USB_STORAGE
110#else
111#undef CONFIG_MUSB_HCD
112#undef CONFIG_CMD_USB
113#undef CONFIG_USB_STORAGE
114#endif
115
116#define CONFIG_CRC32_VERIFY
117#define CONFIG_MX_CYCLIC
118
119/* U-Boot general configuration */
120#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
121#define CONFIG_BOOTFILE "uImage" /* Boot file name */
122#define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */
123#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
124#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
125 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
127#define CONFIG_SYS_HUSH_PARSER
128#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
129#define CONFIG_SYS_LONGHELP
130
Sandeep Paulraj409ec372009-09-08 18:08:06 -0400131#ifdef CONFIG_NAND_DAVINCI
132#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
133#define CONFIG_ENV_IS_IN_NAND
134#define CONFIG_ENV_OFFSET 0x3C0000
135#undef CONFIG_ENV_IS_IN_FLASH
136#endif
David Brownell28b00322009-05-15 23:48:37 +0200137
Sandeep Paulraj409ec372009-09-08 18:08:06 -0400138#define CONFIG_BOOTDELAY 5
David Brownell28b00322009-05-15 23:48:37 +0200139#define CONFIG_BOOTCOMMAND \
140 "dhcp;bootm"
141#define CONFIG_BOOTARGS \
142 "console=ttyS0,115200n8 " \
143 "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
144
145#define CONFIG_CMDLINE_EDITING
146#define CONFIG_VERSION_VARIABLE
147#define CONFIG_TIMESTAMP
148
149#define CONFIG_NET_RETRY_COUNT 10
150
151/* U-Boot memory configuration */
Sandeep Paulraja16df2c2009-09-08 17:09:52 -0400152#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
Sandeep Paulraj409ec372009-09-08 18:08:06 -0400153#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
David Brownell28b00322009-05-15 23:48:37 +0200154#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
155#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
156#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
157
158/* Linux interfacing */
159#define CONFIG_CMDLINE_TAG
160#define CONFIG_SETUP_MEMORY_TAGS
161#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
162#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
163
164
165/* NAND configuration ... socketed with two chipselects. It normally comes
166 * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
167 * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
168 * pretty much demands the 4-bit ECC support.) You can of course swap in
169 * other parts, including small page ones.
170 *
171 * This presents a single read-only partition for all bootloader stuff.
172 * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
173 * some extra space to help cope with bad blocks in that data. Linux
174 * shouldn't care about its detailed layout, and will probably want to use
175 * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to
176 * override this default partitioning using MTDPARTS and cmdlinepart.
177 */
178#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
179
180#ifdef CONFIG_SYS_NAND_LARGEPAGE
181/* Use same layout for 128K/256K blocks; allow some bad blocks */
182#define PART_BOOT "2m(bootloader)ro,"
183#else
184/* Assume 16K erase blocks; allow a few bad ones. */
185#define PART_BOOT "512k(bootloader)ro,"
186#endif
187
188#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
189#define PART_REST "-(filesystem)"
190
191#define MTDPARTS_DEFAULT \
192 "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
193
194#endif /* __CONFIG_H */