blob: 1589913a5e6d9b2309ffda30b34e550bf8b98963 [file] [log] [blame]
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 *
4 * (C) Copyright 2010
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25/*
26 * ve8313 board configuration file
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_E300 1
36#define CONFIG_MPC83xx 1
37#define CONFIG_MPC831x 1
38#define CONFIG_MPC8313 1
39#define CONFIG_VE8313 1
40
41#define CONFIG_PCI 1
42
43#define CONFIG_BOARD_EARLY_INIT_F 1
44
45/*
46 * On-board devices
47 *
48 */
49#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
50
51#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
52
53#define CONFIG_SYS_IMMR 0xE0000000
54
55#define CONFIG_SYS_MEMTEST_START 0x00001000
56#define CONFIG_SYS_MEMTEST_END 0x07000000
57
58#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
59#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
60
61/*
62 * Device configurations
63 */
64
65/*
66 * DDR Setup
67 */
68#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
69#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
70#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
71
72/*
73 * Manually set up DDR parameters, as this board does not
74 * have the SPD connected to I2C.
75 */
76#define CONFIG_SYS_DDR_SIZE 128 /* MB */
77#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
78 | CSCONFIG_AP \
79 | 0x00040000 /* TODO */ \
80 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
81 /* 0x80840102 */
82
83#define CONFIG_SYS_DDR_TIMING_3 0x00000000
84#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
85 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
86 | ( 3 << TIMING_CFG0_RRT_SHIFT ) \
87 | ( 2 << TIMING_CFG0_WWT_SHIFT ) \
88 | ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
89 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
90 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
91 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
92 /* 0x0e720802 */
93#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
94 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
95 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
96 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
97 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
98 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
99 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
100 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
101 /* 0x26256222 */
102#define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
103 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
104 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
105 | ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
106 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
107 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
108 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
109 /* 0x029028c7 */
110#define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
111 | ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
112 /* 0x03202000 */
113#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
114 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
115 | SDRAM_CFG_32_BE )
116 /* 0x43080000 */
117#define CONFIG_SYS_SDRAM_CFG2 0x00401000
118#define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
119 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
120 /* 0x44400232 */
121#define CONFIG_SYS_DDR_MODE_2 0x8000C000
122
123#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124 /*0x02000000*/
125#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
126 | DDRCDR_PZ_NOMZ \
127 | DDRCDR_NZ_NOMZ \
128 | DDRCDR_M_ODR )
129 /* 0x73000002 */
130
131/*
132 * FLASH on the Local Bus
133 */
134#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
135#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
136#define CONFIG_SYS_FLASH_BASE 0xFE000000
137#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
138#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
139#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
140
141#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \
142 (2 << BR_PS_SHIFT) | /* 16 bit */ \
143 BR_V) /* valid */
144#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
145 | OR_GPCM_CSNT \
146 | OR_GPCM_ACS_DIV4 \
147 | OR_GPCM_SCY_5 \
148 | OR_GPCM_TRLX \
149 | OR_GPCM_EAD)
150 /* 0xfe000c55 */
151
152#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
153#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
154
155#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
156#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
157
158#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
159#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
160
161#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
162
163#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
164#define CONFIG_SYS_RAMBOOT
165#endif
166
167#define CONFIG_SYS_INIT_RAM_LOCK 1
168#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
169#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
170
171#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
172#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
173 CONFIG_SYS_GBL_DATA_SIZE)
174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
175
176/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
177#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
178#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
179
180/*
181 * Local Bus LCRR and LBCR regs
182 */
183#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
184#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
185
186#define CONFIG_SYS_LBC_LBCR 0x00040000
187
188#define CONFIG_SYS_LBC_MRTPR 0x20000000
189
190/*
191 * NAND settings
192 */
193#define CONFIG_SYS_NAND_BASE 0x61000000
194#define CONFIG_SYS_MAX_NAND_DEVICE 1
195#define CONFIG_MTD_NAND_VERIFY_WRITE
196#define CONFIG_CMD_NAND 1
197#define CONFIG_NAND_FSL_ELBC 1
198#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
199
200#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
201 | BR_PS_8 \
202 | BR_DECC_CHK_GEN \
203 | BR_MS_FCM \
204 | BR_V ) /* valid */
205 /* 0x61000c21 */
206#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
207 | OR_FCM_BCTLD \
208 | OR_FCM_CHT \
209 | OR_FCM_SCY_2 \
210 | OR_FCM_RST \
211 | OR_FCM_TRLX)
212 /* 0xffff90ac */
213
214#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
215#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
216#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
217#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
218
219#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
220#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
221
222#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
223#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
224
225/* CS2 NvRAM */
226#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
227 | BR_PS_8 \
228 | BR_V)
229 /* 0x60000801 */
230#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
231 | OR_GPCM_CSNT \
232 | OR_GPCM_XACS \
233 | OR_GPCM_SCY_3 \
234 | OR_GPCM_TRLX \
235 | OR_GPCM_EHTR \
236 | OR_GPCM_EAD)
237 /* 0xfffe0937 */
238/* local bus read write buffer mapping SRAM@0x64000000 */
239#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
240 | BR_PS_16 \
241 | BR_V)
242 /* 0x62001001 */
243
244#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
245 | OR_GPCM_CSNT \
246 | OR_GPCM_XACS \
247 | OR_GPCM_SCY_15 \
248 | OR_GPCM_TRLX \
249 | OR_GPCM_EHTR \
250 | OR_GPCM_EAD)
251 /* 0xfe0009f7 */
252
253/* pass open firmware flat tree */
254#define CONFIG_OF_LIBFDT 1
255#define CONFIG_OF_BOARD_SETUP 1
256#define CONFIG_OF_STDOUT_VIA_ALIAS 1
257
258/*
259 * Serial Port
260 */
261#define CONFIG_CONS_INDEX 1
262#define CONFIG_SYS_NS16550
263#define CONFIG_SYS_NS16550_SERIAL
264#define CONFIG_SYS_NS16550_REG_SIZE 1
265#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
266
267#define CONFIG_SYS_BAUDRATE_TABLE \
268 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
269
270#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
271#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
272
273/* Use the HUSH parser */
274#define CONFIG_SYS_HUSH_PARSER
275#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
276
277#if defined(CONFIG_PCI)
278/*
279 * General PCI
280 * Addresses are mapped 1-1.
281 */
282#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
283#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
284#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
285#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
286#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
287#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
288#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
289#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
290#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
291
292#define CONFIG_PCI_PNP /* do pci plug-and-play */
293#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
294#endif
295
296/*
297 * TSEC
298 */
299#define CONFIG_TSEC_ENET /* TSEC ethernet support */
300
301#define CONFIG_NET_MULTI
302
303#define CONFIG_TSEC1
304#ifdef CONFIG_TSEC1
305#define CONFIG_HAS_ETH0
306#define CONFIG_TSEC1_NAME "TSEC1"
307#define CONFIG_SYS_TSEC1_OFFSET 0x24000
308#define TSEC1_PHY_ADDR 0x01
309#define TSEC1_FLAGS 0
310#define TSEC1_PHYIDX 0
311#endif
312
313/* Options are: TSEC[0-1] */
314#define CONFIG_ETHPRIME "TSEC1"
315
316/*
317 * Environment
318 */
319#define CONFIG_ENV_IS_IN_FLASH 1
320#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
321 CONFIG_SYS_MONITOR_LEN)
322#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
323#define CONFIG_ENV_SIZE 0x4000
324/* Address and size of Redundant Environment Sector */
325#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
326 CONFIG_ENV_SECT_SIZE)
327#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
328
329#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
330#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
331
332/*
333 * BOOTP options
334 */
335#define CONFIG_BOOTP_BOOTFILESIZE
336#define CONFIG_BOOTP_BOOTPATH
337#define CONFIG_BOOTP_GATEWAY
338#define CONFIG_BOOTP_HOSTNAME
339
340/*
341 * Command line configuration.
342 */
343#include <config_cmd_default.h>
344
345#define CONFIG_CMD_DHCP
346#define CONFIG_CMD_MII
347#define CONFIG_CMD_PING
348#define CONFIG_CMD_PCI
349
350#define CONFIG_CMDLINE_EDITING 1
351#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
352
353/*
354 * Miscellaneous configurable options
355 */
356#define CONFIG_SYS_LONGHELP /* undef to save memory */
357#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
358#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
359#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
360
361#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
362#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
363#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
364#define CONFIG_SYS_HZ 1000 /* 1ms ticks */
365
366/*
367 * For booting Linux, the board info and command line data
368 * have to be in the first 8 MB of memory, since this is
369 * the maximum mapped by the Linux kernel during initialization.
370 */
371#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
372
373/* 0x64050000 */
374#define CONFIG_SYS_HRCW_LOW (\
375 0x20000000 /* reserved, must be set */ |\
376 HRCWL_DDRCM |\
377 HRCWL_CSB_TO_CLKIN_4X1 | \
378 HRCWL_CORE_TO_CSB_2_5X1)
379
380/* 0xa0600004 */
381#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
382 HRCWH_PCI_ARBITER_ENABLE | \
383 HRCWH_CORE_ENABLE | \
384 HRCWH_FROM_0X00000100 | \
385 HRCWH_BOOTSEQ_DISABLE |\
386 HRCWH_SW_WATCHDOG_DISABLE |\
387 HRCWH_ROM_LOC_LOCAL_16BIT | \
388 HRCWH_TSEC1M_IN_MII | \
389 HRCWH_BIG_ENDIAN | \
390 HRCWH_LALE_EARLY)
391
392/* System IO Config */
393#define CONFIG_SYS_SICRH (0x01000000 | \
394 SICRH_ETSEC2_B | \
395 SICRH_ETSEC2_C | \
396 SICRH_ETSEC2_D | \
397 SICRH_ETSEC2_E | \
398 SICRH_ETSEC2_F | \
399 SICRH_ETSEC2_G | \
400 SICRH_TSOBI1 | \
401 SICRH_TSOBI2)
402 /* 0x010fff03 */
403#define CONFIG_SYS_SICRL (SICRL_LBC | \
404 SICRL_SPI_A | \
405 SICRL_SPI_B | \
406 SICRL_SPI_C | \
407 SICRL_SPI_D | \
408 SICRL_ETSEC2_A)
409 /* 0x33fc0003) */
410
411#define CONFIG_SYS_HID0_INIT 0x000000000
412#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
413 HID0_ENABLE_INSTRUCTION_CACHE)
414
415#define CONFIG_SYS_HID2 HID2_HBE
416
417#define CONFIG_HIGH_BATS 1 /* High BATs supported */
418
419/* DDR @ 0x00000000 */
420#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
421#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
422 BATU_VS | BATU_VP)
423
424#if defined(CONFIG_PCI)
425/* PCI @ 0x80000000 */
426#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
427#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
428 BATU_VS | BATU_VP)
429#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
430 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
431#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
432 BATU_VS | BATU_VP)
433#else
434#define CONFIG_SYS_IBAT1L (0)
435#define CONFIG_SYS_IBAT1U (0)
436#define CONFIG_SYS_IBAT2L (0)
437#define CONFIG_SYS_IBAT2U (0)
438#endif
439
440/* PCI2 not supported on 8313 */
441#define CONFIG_SYS_IBAT3L (0)
442#define CONFIG_SYS_IBAT3U (0)
443#define CONFIG_SYS_IBAT4L (0)
444#define CONFIG_SYS_IBAT4U (0)
445
446/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
447#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
448 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
449#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
450 BATU_VP)
451
452/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
453#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
454#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
455
456/* FPGA, SRAM, NAND @ 0x60000000 */
457#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
458#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
459
460#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
461#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
462#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
463#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
464#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
465#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
466#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
467#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
468#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
469#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
470#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
471#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
472#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
473#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
474#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
475#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
476
477/*
478 * Internal Definitions
479 *
480 * Boot Flags
481 */
482#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
483#define BOOTFLAG_WARM 0x02 /* Software reboot */
484
485#define CONFIG_NETDEV eth0
486
487#define CONFIG_HOSTNAME ve8313
488#define CONFIG_UBOOTPATH ve8313/u-boot.bin
489
490#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
491#define CONFIG_BAUDRATE 115200
492
493#define XMK_STR(x) #x
494#define MK_STR(x) XMK_STR(x)
495
496#define CONFIG_EXTRA_ENV_SETTINGS \
497 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
498 "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \
499 "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
500 "u-boot_addr_r=100000\0" \
501 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
502 "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
503 "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
504 "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
505 " ${filesize};" \
506 "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
507
508#undef MK_STR
509#undef XMK_STR
510
511#endif /* __CONFIG_H */