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Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02001/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02007 */
8
9#include <config.h>
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +053010#include <common.h>
Lei Wena7efd712011-10-18 20:11:42 +053011#include <asm/io.h>
12#include <asm/arch/cpu.h>
Stefan Roese3dc23f72014-10-22 12:13:06 +020013#include <asm/arch/soc.h>
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020014
Stefan Roese81e33f42015-12-21 13:56:33 +010015#if defined(CONFIG_ARCH_MVEBU)
16/* Use common XOR definitions for A3x and AXP */
Stefan Roese0ceb2da2015-08-06 14:43:13 +020017#include "../../../drivers/ddr/marvell/axp/xor.h"
18#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
Stefan Roese8a83c652015-08-03 13:15:31 +020019#endif
20
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +053021DECLARE_GLOBAL_DATA_PTR;
22
Stefan Roese96c5f082014-10-22 12:13:13 +020023struct sdram_bank {
Holger Brunckcf37c5d2012-07-20 02:34:24 +000024 u32 win_bar;
25 u32 win_sz;
26};
27
Stefan Roese96c5f082014-10-22 12:13:13 +020028struct sdram_addr_dec {
29 struct sdram_bank sdram_bank[4];
Holger Brunckcf37c5d2012-07-20 02:34:24 +000030};
31
Stefan Roese96c5f082014-10-22 12:13:13 +020032#define REG_CPUCS_WIN_ENABLE (1 << 0)
33#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
34#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
35#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
Gerlando Falauto45515162012-07-20 02:34:25 +000036
Stefan Roesea8b57a92015-08-10 15:11:27 +020037#define SDRAM_SIZE_MAX 0xc0000000
38
Stefan Roese0ceb2da2015-08-06 14:43:13 +020039#define SCRUB_MAGIC 0xbeefdead
40
41#define SCRB_XOR_UNIT 0
42#define SCRB_XOR_CHAN 1
43#define SCRB_XOR_WIN 0
44
45#define XEBARX_BASE_OFFS 16
46
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020047/*
Stefan Roese96c5f082014-10-22 12:13:13 +020048 * mvebu_sdram_bar - reads SDRAM Base Address Register
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020049 */
Stefan Roese96c5f082014-10-22 12:13:13 +020050u32 mvebu_sdram_bar(enum memory_bank bank)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020051{
Stefan Roese96c5f082014-10-22 12:13:13 +020052 struct sdram_addr_dec *base =
53 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020054 u32 result = 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000055 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020056
57 if ((!enable) || (bank > BANK3))
58 return 0;
59
Holger Brunckcf37c5d2012-07-20 02:34:24 +000060 result = readl(&base->sdram_bank[bank].win_bar);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020061 return result;
62}
63
64/*
Stefan Roese96c5f082014-10-22 12:13:13 +020065 * mvebu_sdram_bs_set - writes SDRAM Bank size
Gerlando Falauto45515162012-07-20 02:34:25 +000066 */
Stefan Roese96c5f082014-10-22 12:13:13 +020067static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
Gerlando Falauto45515162012-07-20 02:34:25 +000068{
Stefan Roese96c5f082014-10-22 12:13:13 +020069 struct sdram_addr_dec *base =
70 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Gerlando Falauto45515162012-07-20 02:34:25 +000071 /* Read current register value */
72 u32 reg = readl(&base->sdram_bank[bank].win_sz);
73
74 /* Clear window size */
Stefan Roese96c5f082014-10-22 12:13:13 +020075 reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
Gerlando Falauto45515162012-07-20 02:34:25 +000076
77 /* Set new window size */
Stefan Roese96c5f082014-10-22 12:13:13 +020078 reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
Gerlando Falauto45515162012-07-20 02:34:25 +000079
80 writel(reg, &base->sdram_bank[bank].win_sz);
81}
82
83/*
Stefan Roese96c5f082014-10-22 12:13:13 +020084 * mvebu_sdram_bs - reads SDRAM Bank size
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020085 */
Stefan Roese96c5f082014-10-22 12:13:13 +020086u32 mvebu_sdram_bs(enum memory_bank bank)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020087{
Stefan Roese96c5f082014-10-22 12:13:13 +020088 struct sdram_addr_dec *base =
89 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020090 u32 result = 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000091 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020092
93 if ((!enable) || (bank > BANK3))
94 return 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000095 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020096 result += 0x01000000;
97 return result;
98}
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +053099
Stefan Roese96c5f082014-10-22 12:13:13 +0200100void mvebu_sdram_size_adjust(enum memory_bank bank)
Gerlando Falautob3168f42012-07-25 06:23:48 +0000101{
102 u32 size;
103
104 /* probe currently equipped RAM size */
Stefan Roese96c5f082014-10-22 12:13:13 +0200105 size = get_ram_size((void *)mvebu_sdram_bar(bank),
106 mvebu_sdram_bs(bank));
Gerlando Falautob3168f42012-07-25 06:23:48 +0000107
108 /* adjust SDRAM window size accordingly */
Stefan Roese96c5f082014-10-22 12:13:13 +0200109 mvebu_sdram_bs_set(bank, size);
Gerlando Falautob3168f42012-07-25 06:23:48 +0000110}
111
Stefan Roese81e33f42015-12-21 13:56:33 +0100112#if defined(CONFIG_ARCH_MVEBU)
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200113static u32 xor_ctrl_save;
114static u32 xor_base_save;
115static u32 xor_mask_save;
116
117static void mv_xor_init2(u32 cs)
118{
119 u32 reg, base, size, base2;
120 u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
121
122 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
123 SCRB_XOR_CHAN));
124 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
125 SCRB_XOR_WIN));
126 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
127 SCRB_XOR_WIN));
128
129 /* Enable Window x for each CS */
130 reg = 0x1;
131 reg |= (0x3 << 16);
132 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
133
134 base = 0;
135 size = mvebu_sdram_bs(cs) - 1;
136 if (size) {
137 base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
138 bank_attr[cs];
139 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
140 base2);
141
142 base += size + 1;
143 size = (size / (64 << 10)) << 16;
144 /* Window x - size - 256 MB */
145 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
146 }
147
148 mv_xor_hal_init(0);
149
150 return;
151}
152
153static void mv_xor_finish2(void)
154{
155 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
156 xor_ctrl_save);
157 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
158 xor_base_save);
159 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
160 xor_mask_save);
161}
162
163static void dram_ecc_scrubbing(void)
164{
165 int cs;
166 u32 size, temp;
167 u32 total_mem = 0;
168 u64 total;
169 u32 start_addr;
170
171 /*
172 * The DDR training code from the bin_hdr / SPL already
173 * scrubbed the DDR till 0x1000000. And the main U-Boot
174 * is loaded to an address < 0x1000000. So we need to
175 * skip this range to not re-scrub this area again.
176 */
177 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
178 temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
179 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
180
181 for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
182 size = mvebu_sdram_bs(cs) - 1;
183 if (size == 0)
184 continue;
185
186 total = (u64)size + 1;
187 total_mem += (u32)(total / (1 << 30));
188 start_addr = 0;
189 mv_xor_init2(cs);
190
191 /* Skip first 16 MiB */
192 if (0 == cs) {
193 start_addr = 0x1000000;
194 size -= start_addr;
195 }
196
197 mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size,
198 SCRUB_MAGIC, SCRUB_MAGIC);
199
200 /* Wait for previous transfer completion */
201 while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
202 ;
203
204 mv_xor_finish2();
205 }
206
207 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
208 temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
209 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
210}
211
212static int ecc_enabled(void)
213{
214 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
215 return 1;
216
217 return 0;
218}
219#else
220static void dram_ecc_scrubbing(void)
221{
222}
223
224static int ecc_enabled(void)
225{
226 return 0;
227}
228#endif
229
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530230int dram_init(void)
231{
Stefan Roesea8b57a92015-08-10 15:11:27 +0200232 u64 size = 0;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530233 int i;
234
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530235 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530236 /*
237 * It is assumed that all memory banks are consecutive
238 * and without gaps.
239 * If the gap is found, ram_size will be reported for
240 * consecutive memory only
241 */
Stefan Roesea8b57a92015-08-10 15:11:27 +0200242 if (mvebu_sdram_bar(i) != size)
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530243 break;
244
Stefan Roesed80cca22014-10-22 12:13:05 +0200245 /*
246 * Don't report more than 3GiB of SDRAM, otherwise there is no
247 * address space left for the internal registers etc.
248 */
Stefan Roesea8b57a92015-08-10 15:11:27 +0200249 size += mvebu_sdram_bs(i);
250 if (size > SDRAM_SIZE_MAX)
251 size = SDRAM_SIZE_MAX;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530252 }
Tanmay Upadhyay28e57102010-10-28 20:06:22 +0530253
254 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
255 /* If above loop terminated prematurely, we need to set
256 * remaining banks' start address & size as 0. Otherwise other
257 * u-boot functions and Linux kernel gets wrong values which
258 * could result in crash */
259 gd->bd->bi_dram[i].start = 0;
260 gd->bd->bi_dram[i].size = 0;
261 }
262
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200263
264 if (ecc_enabled())
265 dram_ecc_scrubbing();
266
Stefan Roesea8b57a92015-08-10 15:11:27 +0200267 gd->ram_size = size;
268
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530269 return 0;
270}
271
272/*
273 * If this function is not defined here,
274 * board.c alters dram bank zero configuration defined above.
275 */
276void dram_init_banksize(void)
277{
Stefan Roesea8b57a92015-08-10 15:11:27 +0200278 u64 size = 0;
279 int i;
280
281 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
282 gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
283 gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
284
285 /* Clip the banksize to 1GiB if it exceeds the max size */
286 size += gd->bd->bi_dram[i].size;
287 if (size > SDRAM_SIZE_MAX)
288 mvebu_sdram_bs_set(i, 0x40000000);
289 }
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530290}
Stefan Roese8a83c652015-08-03 13:15:31 +0200291
Stefan Roese81e33f42015-12-21 13:56:33 +0100292#if defined(CONFIG_ARCH_MVEBU)
Stefan Roese8a83c652015-08-03 13:15:31 +0200293void board_add_ram_info(int use_default)
294{
Stefan Roesed718bf22015-12-21 12:36:40 +0100295 struct sar_freq_modes sar_freq;
296
297 get_sar_freq(&sar_freq);
298 printf(" (%d MHz, ", sar_freq.d_clk);
299
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200300 if (ecc_enabled())
Stefan Roesed718bf22015-12-21 12:36:40 +0100301 printf("ECC");
Stefan Roese8a83c652015-08-03 13:15:31 +0200302 else
Stefan Roesed718bf22015-12-21 12:36:40 +0100303 printf("ECC not");
Stefan Roese8a83c652015-08-03 13:15:31 +0200304 printf(" enabled)");
305}
Stefan Roesed718bf22015-12-21 12:36:40 +0100306#endif