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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00002/*
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
Paul Burtona3e80902013-11-11 11:03:26 +00004 * Copyright (C) 2013 Imagination Technologies
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00005 */
6
7#ifndef _MIPS_ASM_MALTA_H
8#define _MIPS_ASM_MALTA_H
9
Paul Burtonbaf37f02013-11-08 11:18:50 +000010#define MALTA_GT_BASE 0x1be00000
11#define MALTA_GT_PCIIO_BASE 0x18000000
12#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000013
Paul Burtonbaf37f02013-11-08 11:18:50 +000014#define MALTA_MSC01_BIU_BASE 0x1bc80000
15#define MALTA_MSC01_PCI_BASE 0x1bd00000
16#define MALTA_MSC01_PBC_BASE 0x1bd40000
17#define MALTA_MSC01_IP1_BASE 0x1bc00000
18#define MALTA_MSC01_IP1_SIZE 0x00400000
19#define MALTA_MSC01_IP2_BASE1 0x10000000
20#define MALTA_MSC01_IP2_SIZE1 0x08000000
21#define MALTA_MSC01_IP2_BASE2 0x18000000
22#define MALTA_MSC01_IP2_SIZE2 0x04000000
23#define MALTA_MSC01_IP3_BASE 0x1c000000
24#define MALTA_MSC01_IP3_SIZE 0x04000000
25#define MALTA_MSC01_PCIMEM_BASE 0x10000000
26#define MALTA_MSC01_PCIMEM_SIZE 0x10000000
27#define MALTA_MSC01_PCIMEM_MAP 0x10000000
28#define MALTA_MSC01_PCIIO_BASE 0x1b000000
29#define MALTA_MSC01_PCIIO_SIZE 0x00800000
30#define MALTA_MSC01_PCIIO_MAP 0x00000000
31#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000032
Paul Burtone0ada632013-11-08 11:18:51 +000033#define MALTA_ASCIIWORD 0x1f000410
34#define MALTA_ASCIIPOS0 0x1f000418
35#define MALTA_ASCIIPOS1 0x1f000420
36#define MALTA_ASCIIPOS2 0x1f000428
37#define MALTA_ASCIIPOS3 0x1f000430
38#define MALTA_ASCIIPOS4 0x1f000438
39#define MALTA_ASCIIPOS5 0x1f000440
40#define MALTA_ASCIIPOS6 0x1f000448
41#define MALTA_ASCIIPOS7 0x1f000450
42
Paul Burtonbaf37f02013-11-08 11:18:50 +000043#define MALTA_RESET_BASE 0x1f000500
44#define GORESET 0x42
Gabor Juhosac129842013-05-22 03:57:41 +000045
Gabor Juhos10473d02013-11-12 16:47:32 +010046#define MALTA_FLASH_BASE 0x1e000000
Gabor Juhos01564312013-05-22 03:57:38 +000047
Paul Burtonbaf37f02013-11-08 11:18:50 +000048#define MALTA_REVISION 0x1fc00010
49#define MALTA_REVISION_CORID_SHF 10
50#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF)
51#define MALTA_REVISION_CORID_CORE_LV 1
52#define MALTA_REVISION_CORID_CORE_FPGA6 14
Gabor Juhos52caee02013-05-22 03:57:39 +000053
Paul Burton81f98bb2013-11-08 11:18:57 +000054#define PCI_CFG_PIIX4_PIRQRCA 0x60
55#define PCI_CFG_PIIX4_PIRQRCB 0x61
56#define PCI_CFG_PIIX4_PIRQRCC 0x62
57#define PCI_CFG_PIIX4_PIRQRCD 0x63
Paul Burtonbea12b72013-11-26 17:45:27 +000058#define PCI_CFG_PIIX4_SERIRQC 0x64
59#define PCI_CFG_PIIX4_GENCFG 0xb0
60
61#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7)
62#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6)
63
64#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
Paul Burton81f98bb2013-11-08 11:18:57 +000065
Paul Burtonba21a452015-01-29 10:38:20 +000066#define PCI_CFG_PIIX4_IDETIM_PRI 0x40
67#define PCI_CFG_PIIX4_IDETIM_SEC 0x42
68
69#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15)
70
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000071#endif /* _MIPS_ASM_MALTA_H */