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Thomas Chouc8a7ba92015-10-09 13:46:34 +08001/*
2 * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <dm.h>
Mugunthan V Nc8336972016-01-16 21:33:58 +05309#include <dm/lists.h>
10#include <dm/device-internal.h>
Thomas Chouc8a7ba92015-10-09 13:46:34 +080011#include <errno.h>
12#include <timer.h>
13
Bin Meng579eb5a2015-11-13 00:11:15 -080014DECLARE_GLOBAL_DATA_PTR;
15
Thomas Chouc8a7ba92015-10-09 13:46:34 +080016/*
Bin Meng435ae762015-11-13 00:11:14 -080017 * Implement a timer uclass to work with lib/time.c. The timer is usually
Bin Meng9ca07eb2015-11-24 13:31:17 -070018 * a 32/64 bits free-running up counter. The get_rate() method is used to get
Thomas Chouc8a7ba92015-10-09 13:46:34 +080019 * the input clock frequency of the timer. The get_count() method is used
Bin Meng9ca07eb2015-11-24 13:31:17 -070020 * to get the current 64 bits count value. If the hardware is counting down,
Thomas Chouc8a7ba92015-10-09 13:46:34 +080021 * the value should be inversed inside the method. There may be no real
22 * tick, and no timer interrupt.
23 */
24
Simon Glass4f051822016-02-24 09:14:48 -070025int notrace timer_get_count(struct udevice *dev, u64 *count)
Thomas Chouc8a7ba92015-10-09 13:46:34 +080026{
27 const struct timer_ops *ops = device_get_ops(dev);
28
29 if (!ops->get_count)
30 return -ENOSYS;
31
32 return ops->get_count(dev, count);
33}
34
Simon Glass4f051822016-02-24 09:14:48 -070035unsigned long notrace timer_get_rate(struct udevice *dev)
Thomas Chouc8a7ba92015-10-09 13:46:34 +080036{
Simon Glass4f051822016-02-24 09:14:48 -070037 struct timer_dev_priv *uc_priv = dev->uclass_priv;
Thomas Chouc8a7ba92015-10-09 13:46:34 +080038
39 return uc_priv->clock_rate;
40}
41
Bin Meng579eb5a2015-11-13 00:11:15 -080042static int timer_pre_probe(struct udevice *dev)
43{
44 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
45
46 uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
47 "clock-frequency", 0);
48
49 return 0;
50}
51
Stephen Warren0a7edce2016-01-06 10:33:03 -070052static int timer_post_probe(struct udevice *dev)
53{
54 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
55
56 if (!uc_priv->clock_rate)
57 return -EINVAL;
58
59 return 0;
60}
61
Bin Meng9ca07eb2015-11-24 13:31:17 -070062u64 timer_conv_64(u32 count)
63{
64 /* increment tbh if tbl has rolled over */
65 if (count < gd->timebase_l)
66 gd->timebase_h++;
67 gd->timebase_l = count;
68 return ((u64)gd->timebase_h << 32) | gd->timebase_l;
69}
70
Mugunthan V Nc8336972016-01-16 21:33:58 +053071int notrace dm_timer_init(void)
72{
73 const void *blob = gd->fdt_blob;
74 struct udevice *dev = NULL;
75 int node;
76 int ret;
77
78 if (gd->timer)
79 return 0;
80
81 /* Check for a chosen timer to be used for tick */
82 node = fdtdec_get_chosen_node(blob, "tick-timer");
83 if (node < 0) {
84 /* No chosen timer, trying first available timer */
Simon Glass3f603cb2016-02-11 13:23:26 -070085 ret = uclass_first_device_err(UCLASS_TIMER, &dev);
Mugunthan V Nc8336972016-01-16 21:33:58 +053086 if (ret)
87 return ret;
Mugunthan V Nc8336972016-01-16 21:33:58 +053088 } else {
89 if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, &dev)) {
90 /*
91 * If the timer is not marked to be bound before
92 * relocation, bind it anyway.
93 */
94 if (node > 0 &&
95 !lists_bind_fdt(gd->dm_root, blob, node, &dev)) {
96 ret = device_probe(dev);
97 if (ret)
98 return ret;
99 }
100 }
101 }
102
103 if (dev) {
104 gd->timer = dev;
105 return 0;
106 }
107
108 return -ENODEV;
109}
110
Thomas Chouc8a7ba92015-10-09 13:46:34 +0800111UCLASS_DRIVER(timer) = {
112 .id = UCLASS_TIMER,
113 .name = "timer",
Bin Meng579eb5a2015-11-13 00:11:15 -0800114 .pre_probe = timer_pre_probe,
Mugunthan V Na5d80112015-12-24 16:08:06 +0530115 .flags = DM_UC_FLAG_SEQ_ALIAS,
Stephen Warren0a7edce2016-01-06 10:33:03 -0700116 .post_probe = timer_post_probe,
Thomas Chouc8a7ba92015-10-09 13:46:34 +0800117 .per_device_auto_alloc_size = sizeof(struct timer_dev_priv),
118};