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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
3 *
4 * This file is based on similar values for other boards found in
5 * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33#undef DEBUG /* General debug */
34
35/*-----------------------------------------------------------------------
36 * High Level Configuration Options
37 * (easy to change)
38 */
39
40#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
41#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
42
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050043#define CONFIG_CPM2 1 /* Has a CPM2 */
44
wdenke2211742002-11-02 23:30:20 +000045/*-----------------------------------------------------------------------
46 * select serial console configuration
47 *
48 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
49 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
50 * for SCC).
51 *
52 * if CONFIG_CONS_NONE is defined, then the serial console routines must
53 * defined elsewhere (for example, on the cogent platform, there are serial
54 * ports on the motherboard which are used for the serial console - see
55 * cogent/cma101/serial.[ch]).
56 */
57#define CONFIG_CONS_ON_SMC /* define if console on SMC */
58#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
59#undef CONFIG_CONS_NONE /* define if console on something else */
60#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
61
62/*-----------------------------------------------------------------------
63 * select ethernet configuration
64 *
65 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
66 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
67 * for FCC)
68 *
69 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
70 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
71 * from CONFIG_COMMANDS to remove support for networking.
72 */
73#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
74#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
75#undef CONFIG_ETHER_NONE /* define if ether on something else */
76#define CONFIG_ETHER_INDEX 3 /* which channel for ether */
77
78#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
79
80/*-----------------------------------------------------------------------
81 * - Rx-CLK is CLK14
82 * - Tx-CLK is CLK16
83 * - Select bus for bd/buffers (see 28-13)
84 * - Half duplex
85 */
86# define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
87# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
88# define CFG_CPMFCR_RAMTYPE 0
89# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
90
91#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
92
93/* other options */
94
95#define CONFIG_8260_CLKIN 66666666 /* in Hz */
96#define CONFIG_BAUDRATE 19200
97
98#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
99
100/*
101 * select i2c support configuration
102 *
103 * Supported configurations are {none, software, hardware} drivers.
104 * If the software driver is chosen, there are some additional
105 * configuration items that the driver uses to drive the port pins.
106 */
107#undef CONFIG_HARD_I2C /* I2C with hardware support */
108#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
109#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
110#define CFG_I2C_SLAVE 0x7F
111
112/*
113 * Software (bit-bang) I2C driver configuration
114 */
115#ifdef CONFIG_SOFT_I2C
116#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
117#define I2C_ACTIVE (iop->pdir |= 0x00010000)
118#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
119#define I2C_READ ((iop->pdat & 0x00010000) != 0)
120#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
121 else iop->pdat &= ~0x00010000
122#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
123 else iop->pdat &= ~0x00020000
124#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
125#endif /* CONFIG_SOFT_I2C */
126
127#define CONFIG_COMMANDS CONFIG_CMD_DFL
128
129/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
130#include <cmd_confdefs.h>
131
132
133#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
134#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
135#define CONFIG_BOOTARGS "root=/dev/ram rw"
136
137#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
138#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
139#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
140#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
141#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
142#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
143#endif
144
145#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
146
147/*-----------------------------------------------------------------------
148 * Miscellaneous configurable options
149 */
150#define CFG_LONGHELP /* undef to save memory */
151#define CFG_PROMPT "=> " /* Monitor Command Prompt */
152#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
153#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
154#else
155#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
156#endif
157#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
158#define CFG_MAXARGS 16 /* max number of command args */
159#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
160
161#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
162#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
163
164#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
165 /* for versions < 2.4.5-pre5 */
166
167#define CFG_LOAD_ADDR 0x100000 /* default load address */
168
169#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
170
171#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
172
173#define CFG_RESET_ADDRESS 0x04400000
174
175#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
176
177/*-----------------------------------------------------------------------
178 * For booting Linux, the board info and command line data
179 * have to be in the first 8 MB of memory, since this is
180 * the maximum mapped by the Linux kernel during initialization.
181 */
182#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
183
184/*-----------------------------------------------------------------------
185 * Start addresses for the final memory configuration (Setup by the
186 * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
187 */
188#define CFG_SDRAM_BASE 0x00000000
189#define CFG_FLASH_BASE 0xFF800000
190
191#define CFG_MONITOR_BASE TEXT_BASE
192#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
193#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
194
195/*-----------------------------------------------------------------------
196 * FLASH organization
197 */
198#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
199#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
200#define CFG_MAX_FLASH_SIZE (CFG_MAX_FLASH_SECT * 0x10000) /* 4 MB */
201
202#define CFG_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
203#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
204
205/* Environment in FLASH, there is little space left in Serial EEPROM */
206#define CFG_ENV_IS_IN_FLASH 1
207#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
208#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x10000) /* 2. sector */
209
210
211/*-----------------------------------------------------------------------
212 * Hard Reset Configuration Words
213 *
214 * if you change bits in the HRCW, you must also change the CFG_*
215 * defines for the various registers affected by the HRCW e.g. changing
216 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
217 */
218#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
219 ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
220 ( HRCW_MMR11 | HRCW_APPC10 ) |\
221 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
222 ) /* 0x14863245 */
223
224/* no slaves */
225#define CFG_HRCW_SLAVE1 0
226#define CFG_HRCW_SLAVE2 0
227#define CFG_HRCW_SLAVE3 0
228#define CFG_HRCW_SLAVE4 0
229#define CFG_HRCW_SLAVE5 0
230#define CFG_HRCW_SLAVE6 0
231#define CFG_HRCW_SLAVE7 0
232
233/*-----------------------------------------------------------------------
234 * Internal Memory Mapped Register
235 */
236#define CFG_IMMR 0xFF000000 /* We keep original value */
237
238/*-----------------------------------------------------------------------
239 * Definitions for initial stack pointer and data area (in DPRAM)
240 */
241#define CFG_INIT_RAM_ADDR CFG_IMMR
242#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
243#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
244#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
245#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
246
247/*-----------------------------------------------------------------------
248 * Internal Definitions
249 *
250 * Boot Flags
251 */
252#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
253#define BOOTFLAG_WARM 0x02 /* Software reboot */
254
255
256/*-----------------------------------------------------------------------
257 * Cache Configuration
258 */
259#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
260#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
261# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
262#endif
263
264/*-----------------------------------------------------------------------
265 * HIDx - Hardware Implementation-dependent Registers 2-11
266 *-----------------------------------------------------------------------
267 * HID0 also contains cache control.
268 *
269 * HID1 has only read-only information - nothing to set.
270 */
271#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
272 HID0_IFEM|HID0_ABE)
273#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
274#define CFG_HID2 0
275
276/*-----------------------------------------------------------------------
277 * RMR - Reset Mode Register 5-5
278 *-----------------------------------------------------------------------
279 * turn on Checkstop Reset Enable
280 */
281#define CFG_RMR RMR_CSRE
282
283/*-----------------------------------------------------------------------
284 * BCR - Bus Configuration 4-25
285 *-----------------------------------------------------------------------
286 */
287#define CFG_BCR 0xA01C0000
288
289/*-----------------------------------------------------------------------
290 * SIUMCR - SIU Module Configuration 4-31
291 *-----------------------------------------------------------------------
292 */
293#define CFG_SIUMCR 0X4205C000
294
295/*-----------------------------------------------------------------------
296 * SYPCR - System Protection Control 4-35
297 * SYPCR can only be written once after reset!
298 *-----------------------------------------------------------------------
299 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
300 */
301#if defined (CONFIG_WATCHDOG)
302#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
303 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
304#else
305#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
306 SYPCR_SWRI|SYPCR_SWP)
307#endif /* CONFIG_WATCHDOG */
308
309/*-----------------------------------------------------------------------
310 * TMCNTSC - Time Counter Status and Control 4-40
311 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
312 * and enable Time Counter
313 *-----------------------------------------------------------------------
314 */
315#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
316
317/*-----------------------------------------------------------------------
318 * PISCR - Periodic Interrupt Status and Control 4-42
319 *-----------------------------------------------------------------------
320 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
321 * Periodic timer
322 */
323#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
324
325/*-----------------------------------------------------------------------
326 * SCCR - System Clock Control 9-8
327 *-----------------------------------------------------------------------
328 * Ensure DFBRG is Divide by 16
329 */
330#define CFG_SCCR 0
331
332/*-----------------------------------------------------------------------
333 * RCCR - RISC Controller Configuration 13-7
334 *-----------------------------------------------------------------------
335 */
336#define CFG_RCCR 0
337
338/*-----------------------------------------------------------------------
339 * Init Memory Controller:
340 *
341 * Bank Bus Machine PortSz Device
342 * ---- --- ------- ------ ------
343 * 0 60x GPCM 64 bit FLASH
344 * 1 60x SDRAM 64 bit SDRAM
345 */
346
347#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
348#define CFG_OR0_PRELIM 0xFF800882
349#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
350#define CFG_OR1_PRELIM 0xF8002CD0
351
352#define CFG_PSDMR 0x404A241A
353#define CFG_MPTPR 0x00007400
354#define CFG_PSRT 0x00000007
355
356#endif /* __CONFIG_H */