blob: 406fb132aea131188b6ed919340e35ad14b9271a [file] [log] [blame]
Chunhe Lan0b2e13d2014-04-14 18:42:06 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <command.h>
9#include <i2c.h>
10#include <netdev.h>
11#include <linux/compiler.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/cache.h>
15#include <asm/immap_85xx.h>
16#include <asm/fsl_law.h>
17#include <asm/fsl_serdes.h>
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080018#include <asm/fsl_liodn.h>
19#include <fm_eth.h>
20
21#include "t4rdb.h"
Chunhe Lanab06b232014-09-12 14:47:09 +080022#include "cpld.h"
Ying Zhang2f66a822016-01-22 12:15:13 +080023#include "../common/vid.h"
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080024
25DECLARE_GLOBAL_DATA_PTR;
26
27int checkboard(void)
28{
29 struct cpu_type *cpu = gd->arch.cpu;
Chunhe Lanab06b232014-09-12 14:47:09 +080030 u8 sw;
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080031
32 printf("Board: %sRDB, ", cpu->name);
Chunhe Lanab06b232014-09-12 14:47:09 +080033 printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
34 CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
35
36 sw = CPLD_READ(vbank);
37 sw = sw & CPLD_BANK_SEL_MASK;
38
39 if (sw <= 7)
40 printf("vBank: %d\n", sw);
41 else
42 printf("Unsupported Bank=%x\n", sw);
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080043
44 puts("SERDES Reference Clocks:\n");
45 printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
46 " SERDES3=100MHz SERDES4=100MHz\n");
47
48 return 0;
49}
50
51int board_early_init_r(void)
52{
53 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun9d045682014-06-24 21:16:20 -070054 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080055
56 /*
57 * Remap Boot flash + PROMJET region to caching-inhibited
58 * so that flash can be erased properly.
59 */
60
61 /* Flush d-cache and invalidate i-cache of any FLASH data */
62 flush_dcache();
63 invalidate_icache();
64
York Sun9d045682014-06-24 21:16:20 -070065 if (flash_esel == -1) {
66 /* very unlikely unless something is messed up */
67 puts("Error: Could not find TLB for FLASH BASE\n");
68 flash_esel = 2; /* give our best effort to continue */
69 } else {
70 /* invalidate existing TLB entry for flash + promjet */
71 disable_tlb(flash_esel);
72 }
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080073
74 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, flash_esel, BOOKE_PAGESZ_256M, 1);
77
Ying Zhang2f66a822016-01-22 12:15:13 +080078 /*
79 * Adjust core voltage according to voltage ID
80 * This function changes I2C mux to channel 2.
81 */
82 if (adjust_vdd(0))
83 printf("Warning: Adjusting core voltage failed.\n");
84
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080085 return 0;
86}
87
88int misc_init_r(void)
89{
90 return 0;
91}
92
Simon Glasse895a4b2014-10-23 18:58:47 -060093int ft_board_setup(void *blob, bd_t *bd)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080094{
95 phys_addr_t base;
96 phys_size_t size;
97
98 ft_cpu_setup(blob, bd);
99
100 base = getenv_bootm_low();
101 size = getenv_bootm_size();
102
103 fdt_fixup_memory(blob, (u64)base, (u64)size);
104
105#ifdef CONFIG_PCI
106 pci_of_setup(blob, bd);
107#endif
108
109 fdt_fixup_liodn(blob);
110 fdt_fixup_dr_usb(blob, bd);
111
112#ifdef CONFIG_SYS_DPAA_FMAN
113 fdt_fixup_fman_ethernet(blob);
114 fdt_fixup_board_enet(blob);
115#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600116
117 return 0;
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800118}
119
120/*
121 * This function is called by bdinfo to print detail board information.
122 * As an exmaple for future board, we organize the messages into
123 * several sections. If applicable, the message is in the format of
124 * <name> = <value>
125 * It should aligned with normal output of bdinfo command.
126 *
127 * Voltage: Core, DDR and another configurable voltages
128 * Clock : Critical clocks which are not printed already
129 * RCW : RCW source if not printed already
130 * Misc : Other important information not in above catagories
131 */
132void board_detail(void)
133{
134 int rcwsrc;
135
136 /* RCW section SW3[4] */
137 rcwsrc = 0x0;
138 puts("RCW source = ");
139 switch (rcwsrc & 0x1) {
140 case 0x1:
141 puts("SDHC/eMMC\n");
142 break;
143 default:
144 puts("I2C normal addressing\n");
145 break;
146 }
147}