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Marek Vasutd5914012011-01-19 04:40:37 +00001/*
Matt Sealeyfdd63c92012-08-27 05:58:30 +00002 * Copyright (C) 2009 Freescale Semiconductor, Inc.
Marek Vasutd5914012011-01-19 04:40:37 +00003 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
Matt Sealeyfdd63c92012-08-27 05:58:30 +00004 * Copyright (C) 2009-2012 Genesi USA, Inc.
Marek Vasutd5914012011-01-19 04:40:37 +00005 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Marek Vasutd5914012011-01-19 04:40:37 +00007 */
8
9#include <common.h>
10#include <asm/io.h>
Matt Sealeyfdd63c92012-08-27 05:58:30 +000011#include <asm/arch/iomux-mx51.h>
Stefano Babice70a1062011-08-21 10:53:32 +020012#include <asm/gpio.h>
Marek Vasutd5914012011-01-19 04:40:37 +000013#include <asm/errno.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/arch/crm_regs.h>
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +000016#include <asm/arch/clock.h>
Marek Vasutd5914012011-01-19 04:40:37 +000017#include <i2c.h>
18#include <mmc.h>
19#include <fsl_esdhc.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000020#include <power/pmic.h>
Marek Vasutd5914012011-01-19 04:40:37 +000021#include <fsl_pmic.h>
22#include <mc13892.h>
23
24DECLARE_GLOBAL_DATA_PTR;
25
26/*
27 * Compile-time error checking
28 */
29#ifndef CONFIG_MXC_SPI
30#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
31#endif
32
33/*
Matt Sealeyfdd63c92012-08-27 05:58:30 +000034 * Board revisions
35 *
36 * Note that we get these revisions here for convenience, but we only set
37 * up for the production model Smarttop (1.3) and Smartbook (2.0).
38 *
Marek Vasutd5914012011-01-19 04:40:37 +000039 */
Marek Vasutd5914012011-01-19 04:40:37 +000040#define EFIKAMX_BOARD_REV_11 0x1
41#define EFIKAMX_BOARD_REV_12 0x2
42#define EFIKAMX_BOARD_REV_13 0x3
43#define EFIKAMX_BOARD_REV_14 0x4
44
Marek Vasutaf708cb2011-09-25 09:55:43 +000045#define EFIKASB_BOARD_REV_13 0x1
46#define EFIKASB_BOARD_REV_20 0x2
47
Marek Vasutd5914012011-01-19 04:40:37 +000048/*
49 * Board identification
50 */
Matt Sealeyfdd63c92012-08-27 05:58:30 +000051static u32 get_mx_rev(void)
Marek Vasutd5914012011-01-19 04:40:37 +000052{
53 u32 rev = 0;
54 /*
55 * Retrieve board ID:
Matt Sealeyfdd63c92012-08-27 05:58:30 +000056 *
57 * gpio: 16 17 11
58 * ==============
59 * r1.1: 1+ 1 1
60 * r1.2: 1 1 0
61 * r1.3: 1 0 1
62 * r1.4: 1 0 0
63 *
64 * + note: r1.1 does not strap this pin properly so it needs to
65 * be hacked or ignored.
Marek Vasutd5914012011-01-19 04:40:37 +000066 */
Marek Vasutd5914012011-01-19 04:40:37 +000067
Matt Sealeyfdd63c92012-08-27 05:58:30 +000068 /* set to 1 in order to get correct value on board rev 1.1 */
Stefano Babicac966aa2012-08-28 03:10:51 +000069 gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
70 gpio_direction_input(IMX_GPIO_NR(3, 11));
71 gpio_direction_input(IMX_GPIO_NR(3, 16));
72 gpio_direction_input(IMX_GPIO_NR(3, 17));
Marek Vasutd5914012011-01-19 04:40:37 +000073
Stefano Babicac966aa2012-08-28 03:10:51 +000074 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
75 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
76 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
Marek Vasutd5914012011-01-19 04:40:37 +000077
78 return (~rev & 0x7) + 1;
79}
80
Eric Nelson6e142322012-10-03 07:26:38 +000081static iomux_v3_cfg_t const efikasb_revision_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +000082 MX51_PAD_EIM_CS3__GPIO2_28,
83 MX51_PAD_EIM_CS4__GPIO2_29,
84};
85
86static inline u32 get_sb_rev(void)
Marek Vasutaf708cb2011-09-25 09:55:43 +000087{
88 u32 rev = 0;
89
Matt Sealeyfdd63c92012-08-27 05:58:30 +000090 imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
91 ARRAY_SIZE(efikasb_revision_pads));
Stefano Babicac966aa2012-08-28 03:10:51 +000092 gpio_direction_input(IMX_GPIO_NR(2, 28));
93 gpio_direction_input(IMX_GPIO_NR(2, 29));
Marek Vasutaf708cb2011-09-25 09:55:43 +000094
Stefano Babicac966aa2012-08-28 03:10:51 +000095 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
96 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
Marek Vasutaf708cb2011-09-25 09:55:43 +000097
98 return rev;
99}
100
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000101inline uint32_t get_efikamx_rev(void)
Marek Vasutaf708cb2011-09-25 09:55:43 +0000102{
103 if (machine_is_efikamx())
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000104 return get_mx_rev();
105 else if (machine_is_efikasb())
106 return get_sb_rev();
Marek Vasutaf708cb2011-09-25 09:55:43 +0000107}
108
Marek Vasutd5914012011-01-19 04:40:37 +0000109u32 get_board_rev(void)
110{
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000111 return get_cpu_rev() | (get_efikamx_rev() << 8);
Marek Vasutd5914012011-01-19 04:40:37 +0000112}
113
114/*
115 * DRAM initialization
116 */
117int dram_init(void)
118{
119 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +0000120 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000121 PHYS_SDRAM_1_SIZE);
Marek Vasutd5914012011-01-19 04:40:37 +0000122 return 0;
123}
124
125/*
126 * UART configuration
127 */
Eric Nelson6e142322012-10-03 07:26:38 +0000128static iomux_v3_cfg_t const efikamx_uart_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000129 MX51_PAD_UART1_RXD__UART1_RXD,
130 MX51_PAD_UART1_TXD__UART1_TXD,
131 MX51_PAD_UART1_RTS__UART1_RTS,
132 MX51_PAD_UART1_CTS__UART1_CTS,
133};
Marek Vasutd5914012011-01-19 04:40:37 +0000134
135/*
136 * SPI configuration
137 */
Eric Nelson6e142322012-10-03 07:26:38 +0000138static iomux_v3_cfg_t const efikamx_spi_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000139 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
140 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
141 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
142 MX51_PAD_CSPI1_SS0__GPIO4_24,
143 MX51_PAD_CSPI1_SS1__GPIO4_25,
144 MX51_PAD_GPIO1_6__GPIO1_6,
145};
Marek Vasutd5914012011-01-19 04:40:37 +0000146
Stefano Babicac966aa2012-08-28 03:10:51 +0000147#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
148#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
149#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
Marek Vasutd5914012011-01-19 04:40:37 +0000150
151/*
152 * PMIC configuration
153 */
154#ifdef CONFIG_MXC_SPI
155static void power_init(void)
156{
157 unsigned int val;
158 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200159 struct pmic *p;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000160 int ret;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200161
Łukasz Majewskic7336812012-11-13 03:21:55 +0000162 ret = pmic_init(I2C_PMIC);
163 if (ret)
164 return;
165
166 p = pmic_get("FSL_PMIC");
167 if (!p)
168 return;
Marek Vasutd5914012011-01-19 04:40:37 +0000169
170 /* Write needed to Power Gate 2 register */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200171 pmic_reg_read(p, REG_POWER_MISC, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000172 val &= ~PWGT2SPIEN;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200173 pmic_reg_write(p, REG_POWER_MISC, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000174
175 /* Externally powered */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200176 pmic_reg_read(p, REG_CHARGE, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000177 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200178 pmic_reg_write(p, REG_CHARGE, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000179
180 /* power up the system first */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200181 pmic_reg_write(p, REG_POWER_MISC, PWUP);
Marek Vasutd5914012011-01-19 04:40:37 +0000182
183 /* Set core voltage to 1.1V */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200184 pmic_reg_read(p, REG_SW_0, &val);
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000185 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200186 pmic_reg_write(p, REG_SW_0, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000187
188 /* Setup VCC (SW2) to 1.25 */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200189 pmic_reg_read(p, REG_SW_1, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000190 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200191 pmic_reg_write(p, REG_SW_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000192
193 /* Setup 1V2_DIG1 (SW3) to 1.25 */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200194 pmic_reg_read(p, REG_SW_2, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000195 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200196 pmic_reg_write(p, REG_SW_2, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000197 udelay(50);
198
199 /* Raise the core frequency to 800MHz */
200 writel(0x0, &mxc_ccm->cacrr);
201
202 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
203 /* Setup the switcher mode for SW1 & SW2*/
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200204 pmic_reg_read(p, REG_SW_4, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000205 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
206 (SWMODE_MASK << SWMODE2_SHIFT)));
207 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
208 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200209 pmic_reg_write(p, REG_SW_4, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000210
211 /* Setup the switcher mode for SW3 & SW4 */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200212 pmic_reg_read(p, REG_SW_5, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000213 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
214 (SWMODE_MASK << SWMODE4_SHIFT)));
215 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
216 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200217 pmic_reg_write(p, REG_SW_5, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000218
Marek Vasut55723952011-09-28 02:19:57 +0000219 /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200220 pmic_reg_read(p, REG_SETTING_0, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000221 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
Marek Vasut55723952011-09-28 02:19:57 +0000222 val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200223 pmic_reg_write(p, REG_SETTING_0, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000224
225 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200226 pmic_reg_read(p, REG_SETTING_1, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000227 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
Marek Vasut55723952011-09-28 02:19:57 +0000228 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200229 pmic_reg_write(p, REG_SETTING_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000230
Marek Vasut55723952011-09-28 02:19:57 +0000231 /* Enable VGEN1, VGEN2, VDIG, VPLL */
232 pmic_reg_read(p, REG_MODE_0, &val);
233 val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
234 pmic_reg_write(p, REG_MODE_0, val);
235
Marek Vasutd5914012011-01-19 04:40:37 +0000236 /* Configure VGEN3 and VCAM regulators to use external PNP */
237 val = VGEN3CONFIG | VCAMCONFIG;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200238 pmic_reg_write(p, REG_MODE_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000239 udelay(200);
240
241 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
242 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
Marek Vasut55723952011-09-28 02:19:57 +0000243 VVIDEOEN | VAUDIOEN | VSDEN;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200244 pmic_reg_write(p, REG_MODE_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000245
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200246 pmic_reg_read(p, REG_POWER_CTL2, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000247 val |= WDIRESET;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200248 pmic_reg_write(p, REG_POWER_CTL2, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000249
250 udelay(2500);
251}
252#else
253static inline void power_init(void) { }
254#endif
255
256/*
257 * MMC configuration
258 */
259#ifdef CONFIG_FSL_ESDHC
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000260
Marek Vasutd5914012011-01-19 04:40:37 +0000261struct fsl_esdhc_cfg esdhc_cfg[2] = {
Benoît Thébaudeau16e43f32012-08-13 07:28:16 +0000262 {MMC_SDHC1_BASE_ADDR},
263 {MMC_SDHC2_BASE_ADDR},
Marek Vasutd5914012011-01-19 04:40:37 +0000264};
265
Eric Nelson6e142322012-10-03 07:26:38 +0000266static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000267 MX51_PAD_SD1_CMD__SD1_CMD,
268 MX51_PAD_SD1_CLK__SD1_CLK,
269 MX51_PAD_SD1_DATA0__SD1_DATA0,
270 MX51_PAD_SD1_DATA1__SD1_DATA1,
271 MX51_PAD_SD1_DATA2__SD1_DATA2,
272 MX51_PAD_SD1_DATA3__SD1_DATA3,
273 MX51_PAD_GPIO1_1__SD1_WP,
274};
275
Stefano Babicac966aa2012-08-28 03:10:51 +0000276#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000277
Eric Nelson6e142322012-10-03 07:26:38 +0000278static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000279 MX51_PAD_GPIO1_0__SD1_CD,
Benoît Thébaudeauf49d92a2013-05-03 10:32:25 +0000280 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000281};
282
Stefano Babicac966aa2012-08-28 03:10:51 +0000283#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
284#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000285
Eric Nelson6e142322012-10-03 07:26:38 +0000286static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000287 MX51_PAD_SD2_CMD__SD2_CMD,
288 MX51_PAD_SD2_CLK__SD2_CLK,
289 MX51_PAD_SD2_DATA0__SD2_DATA0,
290 MX51_PAD_SD2_DATA1__SD2_DATA1,
291 MX51_PAD_SD2_DATA2__SD2_DATA2,
292 MX51_PAD_SD2_DATA3__SD2_DATA3,
293 MX51_PAD_GPIO1_7__SD2_WP,
294 MX51_PAD_GPIO1_8__SD2_CD,
295};
296
Stefano Babicac966aa2012-08-28 03:10:51 +0000297#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
298#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000299
300static inline uint32_t efikamx_mmc_getcd(u32 base)
Marek Vasutaf708cb2011-09-25 09:55:43 +0000301{
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000302 if (base == MMC_SDHC1_BASE_ADDR)
303 if (machine_is_efikamx())
304 return EFIKAMX_SDHC1_CD;
305 else
306 return EFIKASB_SDHC1_CD;
Marek Vasutaf708cb2011-09-25 09:55:43 +0000307 else
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000308 return EFIKASB_SDHC2_CD;
Marek Vasutaf708cb2011-09-25 09:55:43 +0000309}
310
Thierry Reding314284b2012-01-02 01:15:36 +0000311int board_mmc_getcd(struct mmc *mmc)
Marek Vasutd5914012011-01-19 04:40:37 +0000312{
313 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000314 uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
315 int ret = !gpio_get_value(cd);
Marek Vasutd5914012011-01-19 04:40:37 +0000316
Thierry Reding314284b2012-01-02 01:15:36 +0000317 return ret;
Marek Vasutd5914012011-01-19 04:40:37 +0000318}
Marek Vasutaf708cb2011-09-25 09:55:43 +0000319
Marek Vasutd5914012011-01-19 04:40:37 +0000320int board_mmc_init(bd_t *bis)
321{
322 int ret;
323
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000324 /*
325 * All Efika MX boards use eSDHC1 with a common write-protect GPIO
326 */
327 imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
328 ARRAY_SIZE(efikamx_sdhc1_pads));
329 gpio_direction_input(EFIKAMX_SDHC1_WP);
Marek Vasutd5914012011-01-19 04:40:37 +0000330
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000331 /*
332 * Smartbook and Smarttop differ on the location of eSDHC1
333 * carrier-detect GPIO
334 */
335 if (machine_is_efikamx()) {
336 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
337 gpio_direction_input(EFIKAMX_SDHC1_CD);
338 } else if (machine_is_efikasb()) {
339 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
340 gpio_direction_input(EFIKASB_SDHC1_CD);
341 }
Marek Vasutd5914012011-01-19 04:40:37 +0000342
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000343 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
344 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
345
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000346 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
Marek Vasutd5914012011-01-19 04:40:37 +0000347
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000348 if (machine_is_efikasb()) {
Marek Vasutd5914012011-01-19 04:40:37 +0000349
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000350 imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
351 ARRAY_SIZE(efikasb_sdhc2_pads));
352 gpio_direction_input(EFIKASB_SDHC2_CD);
353 gpio_direction_input(EFIKASB_SDHC2_WP);
Marek Vasutd5914012011-01-19 04:40:37 +0000354 if (!ret)
355 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
Marek Vasutd5914012011-01-19 04:40:37 +0000356 }
Marek Vasutaf708cb2011-09-25 09:55:43 +0000357
Marek Vasutd5914012011-01-19 04:40:37 +0000358 return ret;
359}
360#endif
361
362/*
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000363 * PATA
Marek Vasutd5914012011-01-19 04:40:37 +0000364 */
Eric Nelson6e142322012-10-03 07:26:38 +0000365static iomux_v3_cfg_t const efikamx_pata_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000366 MX51_PAD_NANDF_WE_B__PATA_DIOW,
367 MX51_PAD_NANDF_RE_B__PATA_DIOR,
368 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
369 MX51_PAD_NANDF_CLE__PATA_RESET_B,
370 MX51_PAD_NANDF_WP_B__PATA_DMACK,
371 MX51_PAD_NANDF_RB0__PATA_DMARQ,
372 MX51_PAD_NANDF_RB1__PATA_IORDY,
373 MX51_PAD_GPIO_NAND__PATA_INTRQ,
374 MX51_PAD_NANDF_CS2__PATA_CS_0,
375 MX51_PAD_NANDF_CS3__PATA_CS_1,
376 MX51_PAD_NANDF_CS4__PATA_DA_0,
377 MX51_PAD_NANDF_CS5__PATA_DA_1,
378 MX51_PAD_NANDF_CS6__PATA_DA_2,
379 MX51_PAD_NANDF_D15__PATA_DATA15,
380 MX51_PAD_NANDF_D14__PATA_DATA14,
381 MX51_PAD_NANDF_D13__PATA_DATA13,
382 MX51_PAD_NANDF_D12__PATA_DATA12,
383 MX51_PAD_NANDF_D11__PATA_DATA11,
384 MX51_PAD_NANDF_D10__PATA_DATA10,
385 MX51_PAD_NANDF_D9__PATA_DATA9,
386 MX51_PAD_NANDF_D8__PATA_DATA8,
387 MX51_PAD_NANDF_D7__PATA_DATA7,
388 MX51_PAD_NANDF_D6__PATA_DATA6,
389 MX51_PAD_NANDF_D5__PATA_DATA5,
390 MX51_PAD_NANDF_D4__PATA_DATA4,
391 MX51_PAD_NANDF_D3__PATA_DATA3,
392 MX51_PAD_NANDF_D2__PATA_DATA2,
393 MX51_PAD_NANDF_D1__PATA_DATA1,
394 MX51_PAD_NANDF_D0__PATA_DATA0,
395};
Marek Vasutd5914012011-01-19 04:40:37 +0000396
397/*
Marek Vasutd98d8bc2011-06-24 21:46:07 +0200398 * EHCI USB
399 */
400#ifdef CONFIG_CMD_USB
401extern void setup_iomux_usb(void);
402#else
403static inline void setup_iomux_usb(void) { }
404#endif
405
406/*
Marek Vasutd5914012011-01-19 04:40:37 +0000407 * LED configuration
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000408 *
409 * Smarttop LED pad config is done in the DCD
410 *
Marek Vasutd5914012011-01-19 04:40:37 +0000411 */
Stefano Babicac966aa2012-08-28 03:10:51 +0000412#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
413#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
414#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
Stefano Babice70a1062011-08-21 10:53:32 +0200415
Eric Nelson6e142322012-10-03 07:26:38 +0000416static iomux_v3_cfg_t const efikasb_led_pads[] = {
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000417 MX51_PAD_GPIO1_3__GPIO1_3,
418 MX51_PAD_EIM_CS0__GPIO2_25,
419};
Stefano Babice70a1062011-08-21 10:53:32 +0200420
Stefano Babicac966aa2012-08-28 03:10:51 +0000421#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
422#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
Marek Vasutd5914012011-01-19 04:40:37 +0000423
424/*
425 * Board initialization
426 */
Marek Vasutd5914012011-01-19 04:40:37 +0000427int board_early_init_f(void)
428{
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000429 if (machine_is_efikasb()) {
430 imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
431 ARRAY_SIZE(efikasb_led_pads));
432 gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
433 gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
434 } else if (machine_is_efikamx()) {
435 /*
436 * Set up GPIO directions for LEDs.
437 * IOMUX has been done in the DCD already.
438 * Turn the red LED on for pre-relocation code.
439 */
440 gpio_direction_output(EFIKAMX_LED_BLUE, 0);
441 gpio_direction_output(EFIKAMX_LED_GREEN, 0);
442 gpio_direction_output(EFIKAMX_LED_RED, 1);
443 }
444
445 /*
446 * Both these pad configurations for UART and SPI are kind of redundant
447 * since they are the Power-On Defaults for the i.MX51. But, it seems we
448 * should make absolutely sure that they are set up correctly.
449 */
450 imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
451 ARRAY_SIZE(efikamx_uart_pads));
452 imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
453 ARRAY_SIZE(efikamx_spi_pads));
454
455 /* not technically required for U-Boot operation but do it anyway. */
456 gpio_direction_input(EFIKAMX_PMIC_IRQ);
457 /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
458 gpio_direction_output(EFIKAMX_SPI_SS0, 0);
459 gpio_direction_output(EFIKAMX_SPI_SS1, 1);
Marek Vasutd5914012011-01-19 04:40:37 +0000460
461 return 0;
462}
463
464int board_init(void)
465{
Marek Vasutd5914012011-01-19 04:40:37 +0000466 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
467
468 return 0;
469}
470
471int board_late_init(void)
472{
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000473 if (machine_is_efikamx()) {
474 /*
475 * Set up Blue LED for "In U-Boot" status.
476 * We're all relocated and ready to U-Boot!
477 */
478 gpio_set_value(EFIKAMX_LED_RED, 0);
479 gpio_set_value(EFIKAMX_LED_GREEN, 0);
480 gpio_set_value(EFIKAMX_LED_BLUE, 1);
481 }
Marek Vasutd5914012011-01-19 04:40:37 +0000482
483 power_init();
484
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000485 imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
486 ARRAY_SIZE(efikamx_pata_pads));
Marek Vasutd98d8bc2011-06-24 21:46:07 +0200487 setup_iomux_usb();
488
Marek Vasutd5914012011-01-19 04:40:37 +0000489 return 0;
490}
491
492int checkboard(void)
493{
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000494 u32 rev = get_efikamx_rev();
Marek Vasutaf708cb2011-09-25 09:55:43 +0000495
Matt Sealeyfdd63c92012-08-27 05:58:30 +0000496 printf("Board: Genesi Efika MX ");
497 if (machine_is_efikamx())
498 printf("Smarttop (1.%i)\n", rev & 0xf);
499 else if (machine_is_efikasb())
500 printf("Smartbook\n");
Marek Vasutd5914012011-01-19 04:40:37 +0000501
502 return 0;
503}