blob: 7b918b558d0fa565f6645487b262ff86398794db [file] [log] [blame]
Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs
3 */
wdenkdb01a2e2004-04-15 23:14:49 +00004/*------------------------------------------------------------------------- */
5/* Function: ext_bus_cntlr_init */
6/* Description: Initializes the External Bus Controller for the external */
7/* peripherals. IMPORTANT: For pass1 this code must run from */
8/* cache since you can not reliably change a peripheral banks */
9/* timing register (pbxap) while running code from that bank. */
10/* For ex., since we are running from ROM on bank 0, we can NOT */
11/* execute the code that modifies bank 0 timings from ROM, so */
12/* we run it from cache. */
13/* */
14/* */
15/* The layout for the PEI JSE board: */
16/* Bank 0 - Flash and SRAM */
17/* Bank 1 - SystemACE */
18/* Bank 2 - not used */
19/* Bank 3 - not used */
20/* Bank 4 - not used */
21/* Bank 5 - not used */
22/* Bank 6 - not used */
23/* Bank 7 - not used */
24/*------------------------------------------------------------------------- */
Stefan Roeseb36df562010-09-09 19:18:00 +020025#include <asm/ppc4xx.h>
wdenkdb01a2e2004-04-15 23:14:49 +000026
27#include <ppc_asm.tmpl>
28#include <ppc_defs.h>
29
30#include <asm/cache.h>
31#include <asm/mmu.h>
32
wdenkdb01a2e2004-04-15 23:14:49 +000033 .globl ext_bus_cntlr_init
34ext_bus_cntlr_init:
35 mflr r4 /* save link register */
36 bl ..getAddr
37..getAddr:
38 mflr r3 /* get address of ..getAddr */
39 mtlr r4 /* restore link register */
40 addi r4,0,14 /* set ctr to 10; used to prefetch */
41 mtctr r4 /* 10 cache lines to fit this function */
42 /* in cache (gives us 8x10=80 instrctns) */
43..ebcloop:
44 icbt r0,r3 /* prefetch cache line for addr in r3 */
45 addi r3,r3,32 /* move to next cache line */
46 bdnz ..ebcloop /* continue for 10 cache lines */
47
48 /*----------------------------------------------------------------- */
49 /* Delay to ensure all accesses to ROM are complete before changing */
50 /* bank 0 timings. 200usec should be enough. */
51 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
52 /*----------------------------------------------------------------- */
53 addis r3,0,0x0
54 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
55 mtctr r3
56..spinlp:
57 bdnz ..spinlp /* spin loop */
58
59 /*----------------------------------------------------------------- */
60 /* Memory Bank 0 (Flash) initialization */
61 /*----------------------------------------------------------------- */
62
Stefan Roesed1c3b272009-09-09 16:25:29 +020063 addi r4,0,PB1AP
64 mtdcr EBC0_CFGADDR,r4
wdenkdb01a2e2004-04-15 23:14:49 +000065 addis r4,0,0x9B01
66 ori r4,r4,0x5480
Stefan Roesed1c3b272009-09-09 16:25:29 +020067 mtdcr EBC0_CFGDATA,r4
wdenkdb01a2e2004-04-15 23:14:49 +000068
Stefan Roesed1c3b272009-09-09 16:25:29 +020069 addi r4,0,PB0CR
70 mtdcr EBC0_CFGADDR,r4
wdenkdb01a2e2004-04-15 23:14:49 +000071 addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
72 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
Stefan Roesed1c3b272009-09-09 16:25:29 +020073 mtdcr EBC0_CFGDATA,r4
wdenkdb01a2e2004-04-15 23:14:49 +000074
75 blr