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TsiChung Liew05316f82008-08-11 13:41:49 +00001/*
2 * Configuation settings for the Freescale MCF54451 EVB board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew05316f82008-08-11 13:41:49 +00008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M54451EVB_H
15#define _M54451EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21#define CONFIG_MCF5445x /* define processor family */
22#define CONFIG_M54451 /* define processor type */
23#define CONFIG_M54451EVB /* M54451EVB board */
24
25#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew05316f82008-08-11 13:41:49 +000027#define CONFIG_BAUDRATE 115200
TsiChung Liew05316f82008-08-11 13:41:49 +000028
29#undef CONFIG_WATCHDOG
30
31#define CONFIG_TIMESTAMP /* Print image info with timestamp */
32
33/*
34 * BOOTP options
35 */
36#define CONFIG_BOOTP_BOOTFILESIZE
37#define CONFIG_BOOTP_BOOTPATH
38#define CONFIG_BOOTP_GATEWAY
39#define CONFIG_BOOTP_HOSTNAME
40
41/* Command line configuration */
42#include <config_cmd_default.h>
43
44#define CONFIG_CMD_BOOTD
45#define CONFIG_CMD_CACHE
46#define CONFIG_CMD_DATE
47#define CONFIG_CMD_DHCP
48#define CONFIG_CMD_ELF
49#define CONFIG_CMD_FLASH
50#define CONFIG_CMD_I2C
51#undef CONFIG_CMD_JFFS2
52#define CONFIG_CMD_MEMORY
53#define CONFIG_CMD_MISC
54#define CONFIG_CMD_MII
55#define CONFIG_CMD_NET
TsiChung Liew709b3842009-06-11 15:39:57 +000056#define CONFIG_CMD_NFS
TsiChung Liew05316f82008-08-11 13:41:49 +000057#define CONFIG_CMD_PING
58#define CONFIG_CMD_REGINFO
59#define CONFIG_CMD_SPI
60#define CONFIG_CMD_SF
61
62#undef CONFIG_CMD_LOADB
63#undef CONFIG_CMD_LOADS
64
65/* Network configuration */
66#define CONFIG_MCFFEC
67#ifdef CONFIG_MCFFEC
TsiChung Liew05316f82008-08-11 13:41:49 +000068# define CONFIG_MII 1
69# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070# define CONFIG_SYS_DISCOVER_PHY
71# define CONFIG_SYS_RX_ETH_BUFFER 8
72# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew05316f82008-08-11 13:41:49 +000073
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074# define CONFIG_SYS_FEC0_PINMUX 0
75# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChung Liew05316f82008-08-11 13:41:49 +000076# define MCFFEC_TOUT_LOOP 50000
77
78# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
TsiChung Liew052c0892009-07-08 07:41:24 +000079# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
TsiChung Liew05316f82008-08-11 13:41:49 +000080# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
81# define CONFIG_ETHPRIME "FEC0"
82# define CONFIG_IPADDR 192.162.1.2
83# define CONFIG_NETMASK 255.255.255.0
84# define CONFIG_SERVERIP 192.162.1.1
85# define CONFIG_GATEWAYIP 192.162.1.1
86# define CONFIG_OVERWRITE_ETHADDR_ONCE
87
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
89# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liew05316f82008-08-11 13:41:49 +000090# define FECDUPLEX FULL
91# define FECSPEED _100BASET
92# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
94# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew05316f82008-08-11 13:41:49 +000095# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liew05316f82008-08-11 13:41:49 +000097#endif
98
99#define CONFIG_HOSTNAME M54451EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liew05316f82008-08-11 13:41:49 +0000101/* ST Micro serial flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_LOAD_ADDR2 0x40010007
TsiChung Liew05316f82008-08-11 13:41:49 +0000103#define CONFIG_EXTRA_ENV_SETTINGS \
104 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200105 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000106 "loadaddr=0x40010000\0" \
107 "sbfhdr=sbfhdr.bin\0" \
108 "uboot=u-boot.bin\0" \
109 "load=tftp ${loadaddr} ${sbfhdr};" \
Marek Vasut5368c552012-09-23 17:41:24 +0200110 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000111 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +0800112 "prog=sf probe 0:1 1000000 3;" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000113 "sf erase 0 30000;" \
114 "sf write ${loadaddr} 0 30000;" \
115 "save\0" \
116 ""
117#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_UBOOT_END 0x3FFFF
TsiChung Liew05316f82008-08-11 13:41:49 +0000119#define CONFIG_EXTRA_ENV_SETTINGS \
120 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200121 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000122 "loadaddr=40010000\0" \
123 "u-boot=u-boot.bin\0" \
124 "load=tftp ${loadaddr) ${u-boot}\0" \
125 "upd=run load; run prog\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200126 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
127 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000128 "cp.b ${loadaddr} 0 ${filesize};" \
129 "save\0" \
130 ""
131#endif
132
133/* Realtime clock */
134#define CONFIG_MCFRTC
135#undef RTC_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
TsiChung Liew05316f82008-08-11 13:41:49 +0000137
138/* Timer */
139#define CONFIG_MCFTMR
140#undef CONFIG_MCFPIT
141
142/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200143#define CONFIG_SYS_I2C
144#define CONFIG_SYS_I2C_FSL
145#define CONFIG_SYS_FSL_I2C_SPEED 80000
146#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
147#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
TsiChung Liew709b3842009-06-11 15:39:57 +0000148#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChung Liew05316f82008-08-11 13:41:49 +0000149
150/* DSPI and Serial Flash */
TsiChung Liewee0a8462009-06-30 14:18:29 +0000151#define CONFIG_CF_SPI
TsiChung Liew05316f82008-08-11 13:41:49 +0000152#define CONFIG_CF_DSPI
153#define CONFIG_SERIAL_FLASH
154#define CONFIG_HARD_SPI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_SBFHDR_SIZE 0x7
TsiChung Liew05316f82008-08-11 13:41:49 +0000156#ifdef CONFIG_CMD_SPI
157# define CONFIG_SPI_FLASH
158# define CONFIG_SPI_FLASH_STMICRO
159
TsiChung Liewee0a8462009-06-30 14:18:29 +0000160# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
161 DSPI_CTAR_PCSSCK_1CLK | \
162 DSPI_CTAR_PASC(0) | \
163 DSPI_CTAR_PDT(0) | \
164 DSPI_CTAR_CSSCK(0) | \
165 DSPI_CTAR_ASC(0) | \
166 DSPI_CTAR_DT(1))
167# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
168# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
TsiChung Liew05316f82008-08-11 13:41:49 +0000169#endif
170
171/* Input, PCI, Flexbus, and VCO */
172#define CONFIG_EXTRA_CLOCK
173
TsiChung Liew709b3842009-06-11 15:39:57 +0000174#define CONFIG_PRAM 2048 /* 2048 KB */
TsiChung Liew05316f82008-08-11 13:41:49 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_PROMPT "-> "
177#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liew05316f82008-08-11 13:41:49 +0000178
179#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChung Liew05316f82008-08-11 13:41:49 +0000181#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChung Liew05316f82008-08-11 13:41:49 +0000183#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
185#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
186#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChung Liew05316f82008-08-11 13:41:49 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
TsiChung Liew05316f82008-08-11 13:41:49 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_HZ 1000
TsiChung Liew05316f82008-08-11 13:41:49 +0000191
TsiChung Liew709b3842009-06-11 15:39:57 +0000192#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liew05316f82008-08-11 13:41:49 +0000193
194/*
195 * Low Level Configuration Settings
196 * (address mappings, register initial values, etc.)
197 * You should know what you are doing if you make changes here.
198 */
199
200/*-----------------------------------------------------------------------
201 * Definitions for initial stack pointer and data area (in DPRAM)
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200204#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200206#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk553f0982010-10-26 13:32:32 +0200208#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
TsiChung Liew05316f82008-08-11 13:41:49 +0000209
210/*-----------------------------------------------------------------------
211 * Start addresses for the final memory configuration
212 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew05316f82008-08-11 13:41:49 +0000214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_SDRAM_BASE 0x40000000
216#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
217#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
218#define CONFIG_SYS_SDRAM_CFG2 0x57670000
219#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
220#define CONFIG_SYS_SDRAM_EMOD 0x80810000
221#define CONFIG_SYS_SDRAM_MODE 0x008D0000
222#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
TsiChung Liew05316f82008-08-11 13:41:49 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
225#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChung Liew05316f82008-08-11 13:41:49 +0000226
227#ifdef CONFIG_CF_SBF
Jason Jin09933fb2011-08-19 10:10:40 +0800228# define CONFIG_SERIAL_BOOT
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200229# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
TsiChung Liew05316f82008-08-11 13:41:49 +0000230#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew05316f82008-08-11 13:41:49 +0000232#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
234#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChung Liew05316f82008-08-11 13:41:49 +0000235
Jason Jin09933fb2011-08-19 10:10:40 +0800236/* Reserve 256 kB for malloc() */
237#define CONFIG_SYS_MALLOC_LEN (256 << 10)
TsiChung Liew05316f82008-08-11 13:41:49 +0000238/*
239 * For booting Linux, the board info and command line data
240 * have to be in the first 8 MB of memory, since this is
241 * the maximum mapped by the Linux kernel during initialization ??
242 */
243/* Initial Memory map for Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew05316f82008-08-11 13:41:49 +0000245
246/* Configuration for environment
Jason Jin09933fb2011-08-19 10:10:40 +0800247 * Environment is not embedded in u-boot. First time runing may have env
248 * crc error warning if there is no correct environment on the flash.
TsiChung Liew05316f82008-08-11 13:41:49 +0000249 */
TsiChung Liew709b3842009-06-11 15:39:57 +0000250#if defined(CONFIG_SYS_STMICRO_BOOT)
Jean-Christophe PLAGNIOL-VILLARD0b5099a2008-09-10 22:48:00 +0200251# define CONFIG_ENV_IS_IN_SPI_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200252# define CONFIG_ENV_SPI_CS 1
253# define CONFIG_ENV_OFFSET 0x20000
254# define CONFIG_ENV_SIZE 0x2000
255# define CONFIG_ENV_SECT_SIZE 0x10000
TsiChung Liew05316f82008-08-11 13:41:49 +0000256#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200257# define CONFIG_ENV_IS_IN_FLASH 1
Jason Jin09933fb2011-08-19 10:10:40 +0800258# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
TsiChung Liew709b3842009-06-11 15:39:57 +0000259# define CONFIG_ENV_SIZE 0x2000
Jason Jin09933fb2011-08-19 10:10:40 +0800260# define CONFIG_ENV_SECT_SIZE 0x20000
TsiChung Liew05316f82008-08-11 13:41:49 +0000261#endif
262#undef CONFIG_ENV_OVERWRITE
TsiChung Liew05316f82008-08-11 13:41:49 +0000263
TsiChung Liewee0a8462009-06-30 14:18:29 +0000264/* FLASH organization */
265#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew05316f82008-08-11 13:41:49 +0000266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_FLASH_CFI
268#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liew05316f82008-08-11 13:41:49 +0000269
270# define CONFIG_FLASH_CFI_DRIVER 1
TsiChung Liew709b3842009-06-11 15:39:57 +0000271# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
273# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
274# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
275# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
276# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
277# define CONFIG_SYS_FLASH_CHECKSUM
278# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
TsiChung Liew05316f82008-08-11 13:41:49 +0000279
280#endif
281
282/*
283 * This is setting for JFFS2 support in u-boot.
284 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
285 */
TsiChung Liew709b3842009-06-11 15:39:57 +0000286#ifdef CONFIG_CMD_JFFS2
TsiChung Liew05316f82008-08-11 13:41:49 +0000287# define CONFIG_JFFS2_DEV "nor0"
288# define CONFIG_JFFS2_PART_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
TsiChung Liew05316f82008-08-11 13:41:49 +0000290#endif
291
TsiChung Liew709b3842009-06-11 15:39:57 +0000292/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew05316f82008-08-11 13:41:49 +0000294
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600295#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200296 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600297#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200298 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600299#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
300#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
301#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
302 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
303 CF_ACR_EN | CF_ACR_SM_ALL)
304#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
305 CF_CACR_ICINVA | CF_CACR_EUSP)
306#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
307 CF_CACR_DEC | CF_CACR_DDCM_P | \
308 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
309
TsiChung Liew05316f82008-08-11 13:41:49 +0000310/*-----------------------------------------------------------------------
311 * Memory bank definitions
312 */
313/*
TsiChung Liew709b3842009-06-11 15:39:57 +0000314 * CS0 - NOR Flash 16MB
TsiChung Liew05316f82008-08-11 13:41:49 +0000315 * CS1 - Available
316 * CS2 - Available
317 * CS3 - Available
318 * CS4 - Available
319 * CS5 - Available
320 */
321
TsiChung Liew709b3842009-06-11 15:39:57 +0000322 /* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_CS0_BASE 0x00000000
TsiChung Liew709b3842009-06-11 15:39:57 +0000324#define CONFIG_SYS_CS0_MASK 0x00FF0001
325#define CONFIG_SYS_CS0_CTRL 0x00004D80
TsiChung Liew05316f82008-08-11 13:41:49 +0000326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew05316f82008-08-11 13:41:49 +0000328
329#endif /* _M54451EVB_H */