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Stefan Roese16c0cc12007-03-21 13:39:57 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese16c0cc12007-03-21 13:39:57 +01006 */
7
8/************************************************************************
9 * acadia.h - configuration for AMCC Acadia (405EZ)
10 ***********************************************************************/
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*-----------------------------------------------------------------------
16 * High Level Configuration Options
17 *----------------------------------------------------------------------*/
Stefan Roese3cb86f32007-03-24 15:45:34 +010018#define CONFIG_ACADIA 1 /* Board is Acadia */
19#define CONFIG_4xx 1 /* ... PPC4xx family */
20#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
Stefan Roese490f2042008-06-06 15:55:03 +020021
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#ifndef CONFIG_SYS_TEXT_BASE
23#define CONFIG_SYS_TEXT_BASE 0xFFF80000
24#endif
25
Stefan Roese490f2042008-06-06 15:55:03 +020026/*
27 * Include common defines/options for all AMCC eval boards
28 */
29#define CONFIG_HOSTNAME acadia
30#include "amcc-common.h"
31
Stefan Roese5d4a1792007-05-24 08:22:09 +020032/* Detect Acadia PLL input clock automatically via CPLD bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
Stefan Roese5d4a1792007-05-24 08:22:09 +020034 66666666 : 33333000)
Stefan Roese16c0cc12007-03-21 13:39:57 +010035
Stefan Roese3cb86f32007-03-24 15:45:34 +010036#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
37#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
Stefan Roese16c0cc12007-03-21 13:39:57 +010038
39#define CONFIG_NO_SERIAL_EEPROM
40/*#undef CONFIG_NO_SERIAL_EEPROM*/
41
42#ifdef CONFIG_NO_SERIAL_EEPROM
Stefan Roese16c0cc12007-03-21 13:39:57 +010043/*----------------------------------------------------------------------------
44 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
45 * assuming a 66MHz input clock to the 405EZ.
46 *---------------------------------------------------------------------------*/
47/* #define PLLMR0_100_100_12 */
48#define PLLMR0_200_133_66
49/* #define PLLMR0_266_160_80 */
50/* #define PLLMR0_333_166_83 */
51#endif
52
53/*-----------------------------------------------------------------------
54 * Base addresses -- Note these are effective addresses where the
55 * actual resources get mapped (not physical addresses)
56 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_FLASH_BASE 0xfe000000
58#define CONFIG_SYS_CPLD_BASE 0x80000000
59#define CONFIG_SYS_NAND_ADDR 0xd0000000
60#define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
Stefan Roese16c0cc12007-03-21 13:39:57 +010061
Stefan Roese3cb86f32007-03-24 15:45:34 +010062/*-----------------------------------------------------------------------
63 * Initial RAM & stack pointer
64 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
Stefan Roese3cb86f32007-03-24 15:45:34 +010066
67/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
69#define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
70#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020071#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Stefan Roese3cb86f32007-03-24 15:45:34 +010072
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020073#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese3cb86f32007-03-24 15:45:34 +010075
76/*-----------------------------------------------------------------------
77 * Serial Port
78 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020079#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
81#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roese3cb86f32007-03-24 15:45:34 +010082
83/*-----------------------------------------------------------------------
84 * Environment
85 *----------------------------------------------------------------------*/
Stefan Roese16c0cc12007-03-21 13:39:57 +010086#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020087#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese16c0cc12007-03-21 13:39:57 +010088#else
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +020089#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020090#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Stefan Roese16c0cc12007-03-21 13:39:57 +010091#endif
92
Stefan Roese3cb86f32007-03-24 15:45:34 +010093/*-----------------------------------------------------------------------
94 * FLASH related
95 *----------------------------------------------------------------------*/
Stefan Roesec440bfe2007-06-06 11:42:13 +020096#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020098#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese3cb86f32007-03-24 15:45:34 +010099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
101#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
102#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
105#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
108#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100109
Stefan Roesec440bfe2007-06-06 11:42:13 +0200110#else
Stefan Roese8a805df2010-09-16 14:01:53 +0200111/*
112 * No NOR-flash on Acadia when NAND-booting. We need to undef the
113 * NOR device-tree fixup code as well, since flash_info is not defined
114 * in this case.
115 */
116#define CONFIG_SYS_NO_FLASH 1
117#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
Stefan Roesec440bfe2007-06-06 11:42:13 +0200118#endif
119
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200120#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200121#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200123#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100124
125/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200126#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
127#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese3cb86f32007-03-24 15:45:34 +0100128#endif
129
Stefan Roesec440bfe2007-06-06 11:42:13 +0200130/*
131 * IPL (Initial Program Loader, integrated inside CPU)
132 * Will load first 4k from NAND (SPL) into cache and execute it from there.
133 *
134 * SPL (Secondary Program Loader)
135 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
136 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
137 * controller and the NAND controller so that the special U-Boot image can be
138 * loaded from NAND to SDRAM.
139 *
140 * NUB (NAND U-Boot)
141 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
142 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
143 *
144 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
145 * set up. While still running from cache, I experienced problems accessing
146 * the NAND controller. sr - 2006-08-25
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
149#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
150#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
151#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
152#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
153#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Stefan Roesec440bfe2007-06-06 11:42:13 +0200154
155/*
156 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
159#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
Stefan Roesec440bfe2007-06-06 11:42:13 +0200160
161/*
162 * Now the NAND chip has to be defined (no autodetection used!)
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
165#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
166#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
167#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
168#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
Stefan Roesec440bfe2007-06-06 11:42:13 +0200169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_NAND_ECCSIZE 256
171#define CONFIG_SYS_NAND_ECCBYTES 3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_NAND_OOBSIZE 16
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Stefan Roesec440bfe2007-06-06 11:42:13 +0200174
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200175#ifdef CONFIG_ENV_IS_IN_NAND
Stefan Roesec440bfe2007-06-06 11:42:13 +0200176/*
177 * For NAND booting the environment is embedded in the U-Boot image. Please take
178 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
181#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200182#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Stefan Roesec440bfe2007-06-06 11:42:13 +0200183#endif
184
Stefan Roese3cb86f32007-03-24 15:45:34 +0100185/*-----------------------------------------------------------------------
186 * RAM (CRAM)
187 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100189
190/*-----------------------------------------------------------------------
191 * I2C
192 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000193#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese3cb86f32007-03-24 15:45:34 +0100194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_I2C_MULTI_EEPROMS
196#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
197#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
198#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
199#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese3cb86f32007-03-24 15:45:34 +0100200
201/* I2C SYSMON (LM75, AD7414 is almost compatible) */
202#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
203#define CONFIG_DTT_AD7414 1 /* use AD7414 */
204#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_DTT_MAX_TEMP 70
206#define CONFIG_SYS_DTT_LOW_TEMP -30
207#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese3cb86f32007-03-24 15:45:34 +0100208
Stefan Roese3cb86f32007-03-24 15:45:34 +0100209/*-----------------------------------------------------------------------
210 * Ethernet
211 *----------------------------------------------------------------------*/
Stefan Roese3cb86f32007-03-24 15:45:34 +0100212#define CONFIG_PHY_ADDR 0 /* PHY address */
Stefan Roesed1c1ba82008-05-08 10:48:58 +0200213#define CONFIG_HAS_ETH0 1
Stefan Roese3cb86f32007-03-24 15:45:34 +0100214
Stefan Roese490f2042008-06-06 15:55:03 +0200215/*
216 * Default environment variables
217 */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100218#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200219 CONFIG_AMCC_DEF_ENV \
Stefan Roese84a45d32009-09-11 17:09:45 +0200220 CONFIG_AMCC_DEF_ENV_POWERPC \
221 CONFIG_AMCC_DEF_ENV_PPC_OLD \
Stefan Roese490f2042008-06-06 15:55:03 +0200222 CONFIG_AMCC_DEF_ENV_NOR_UPD \
223 CONFIG_AMCC_DEF_ENV_NAND_UPD \
Stefan Roese16c0cc12007-03-21 13:39:57 +0100224 "kernel_addr=fff10000\0" \
225 "ramdisk_addr=fff20000\0" \
Stefan Roese16c0cc12007-03-21 13:39:57 +0100226 "kozio=bootm ffc60000\0" \
227 ""
Stefan Roese16c0cc12007-03-21 13:39:57 +0100228
Stefan Roese16c0cc12007-03-21 13:39:57 +0100229#define CONFIG_USB_OHCI
230#define CONFIG_USB_STORAGE
231
Stefan Roese16c0cc12007-03-21 13:39:57 +0100232/* Partitions */
233#define CONFIG_MAC_PARTITION
234#define CONFIG_DOS_PARTITION
235#define CONFIG_ISO_PARTITION
236
237#define CONFIG_SUPPORT_VFAT
238
Jon Loeliger0b361c92007-07-04 22:31:42 -0500239/*
Stefan Roese490f2042008-06-06 15:55:03 +0200240 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500241 */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500242#define CONFIG_CMD_DTT
Jon Loeliger0b361c92007-07-04 22:31:42 -0500243#define CONFIG_CMD_NAND
Jon Loeliger0b361c92007-07-04 22:31:42 -0500244#define CONFIG_CMD_USB
245
246/*
247 * No NOR on Acadia when NAND-booting
248 */
249#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
250#undef CONFIG_CMD_FLASH
251#undef CONFIG_CMD_IMLS
252#endif
253
Stefan Roese16c0cc12007-03-21 13:39:57 +0100254/*-----------------------------------------------------------------------
255 * NAND FLASH
256 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
259#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100260
261/*-----------------------------------------------------------------------
Stefan Roese16c0cc12007-03-21 13:39:57 +0100262 * External Bus Controller (EBC) Setup
Stefan Roese3cb86f32007-03-24 15:45:34 +0100263 *----------------------------------------------------------------------*/
Stefan Roesec440bfe2007-06-06 11:42:13 +0200264#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_NAND_CS 3
Stefan Roese3cb86f32007-03-24 15:45:34 +0100266/* Memory Bank 0 (Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_EBC_PB0AP 0x03337200
268#define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100269
Stefan Roesec440bfe2007-06-06 11:42:13 +0200270/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_EBC_PB3AP 0x018003c0
272#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roesec440bfe2007-06-06 11:42:13 +0200273
Stefan Roese3cb86f32007-03-24 15:45:34 +0100274/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
275/* Memory Bank 1 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_EBC_PB1AP 0x030400c0
277#define CONFIG_SYS_EBC_PB1CR 0x000bc000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100278
Stefan Roese3cb86f32007-03-24 15:45:34 +0100279/* Memory Bank 2 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_EBC_PB2AP 0x030400c0
281#define CONFIG_SYS_EBC_PB2CR 0x020bc000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200282#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Stefan Roesec440bfe2007-06-06 11:42:13 +0200284/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_EBC_PB0AP 0x018003c0
286#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese16c0cc12007-03-21 13:39:57 +0100287
Stefan Roesec440bfe2007-06-06 11:42:13 +0200288/*
289 * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
290 * NAND-SPL already initialized the CRAM and EBC to sync mode.
291 */
292/* Memory Bank 1 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
294#define CONFIG_SYS_EBC_PB1CR 0x000bc000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200295
296/* Memory Bank 2 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
298#define CONFIG_SYS_EBC_PB2CR 0x020bc000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200299#endif
Stefan Roese16c0cc12007-03-21 13:39:57 +0100300
Stefan Roese3cb86f32007-03-24 15:45:34 +0100301/* Memory Bank 4 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_EBC_PB4AP 0x04006000
303#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000)
Stefan Roese16c0cc12007-03-21 13:39:57 +0100304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_EBC_CFG 0xf8400000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100306
307/*-----------------------------------------------------------------------
Stefan Roese3cb86f32007-03-24 15:45:34 +0100308 * GPIO Setup
309 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_GPIO_CRAM_CLK 8
311#define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
312#define CONFIG_SYS_GPIO_CRAM_ADV 10
313#define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100314
315/*-----------------------------------------------------------------------
Stefan Roese16c0cc12007-03-21 13:39:57 +0100316 * Definitions for GPIO_0 setup (PPC405EZ specific)
317 *
Stefan Roese5d4a1792007-05-24 08:22:09 +0200318 * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
319 * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
Stefan Roese16c0cc12007-03-21 13:39:57 +0100320 * GPIO0[4] - External Bus Controller Hold Input
321 * GPIO0[5] - External Bus Controller Priority Input
322 * GPIO0[6] - External Bus Controller HLDA Output
323 * GPIO0[7] - External Bus Controller Bus Request Output
324 * GPIO0[8] - CRAM Clk Output
325 * GPIO0[9] - External Bus Controller Ready Input
326 * GPIO0[10] - CRAM Adv Output
327 * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
328 * GPIO0[25] - External DMA Request Input
329 * GPIO0[26] - External DMA EOT I/O
330 * GPIO0[25] - External DMA Ack_n Output
331 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
332 * GPIO0[28-30] - Trace Outputs / PWM Inputs
333 * GPIO0[31] - PWM_8 I/O
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_GPIO0_TCR 0xC0A00000
336#define CONFIG_SYS_GPIO0_OSRL 0x50004400
337#define CONFIG_SYS_GPIO0_OSRH 0x02000055
338#define CONFIG_SYS_GPIO0_ISR1L 0x00001000
339#define CONFIG_SYS_GPIO0_ISR1H 0x00000055
340#define CONFIG_SYS_GPIO0_TSRL 0x02000000
341#define CONFIG_SYS_GPIO0_TSRH 0x00000055
Stefan Roese16c0cc12007-03-21 13:39:57 +0100342
343/*-----------------------------------------------------------------------
344 * Definitions for GPIO_1 setup (PPC405EZ specific)
345 *
346 * GPIO1[0-6] - PWM_9 to PWM_15 I/O
347 * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
348 * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
349 * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
350 * GPIO1[10-12] - UART0 Control Inputs
351 * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
352 * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
353 * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
354 * GPIO1[16] - SPI_SS_1_N Output
355 * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
358#define CONFIG_SYS_GPIO1_OSRL 0x40000110
359#define CONFIG_SYS_GPIO1_OSRH 0x55455555
360#define CONFIG_SYS_GPIO1_ISR1L 0x15555445
361#define CONFIG_SYS_GPIO1_ISR1H 0x00000000
362#define CONFIG_SYS_GPIO1_TSRL 0x00000000
363#define CONFIG_SYS_GPIO1_TSRH 0x00000000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100364
Stefan Roese16c0cc12007-03-21 13:39:57 +0100365#endif /* __CONFIG_H */