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Heiko Schocher5fb2b232008-01-11 15:15:15 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher5fb2b232008-01-11 15:15:15 +01006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10/*
11 * High Level Configuration Options
12 * (easy to change)
13 */
14#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
15#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
16#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
17#define CONFIG_MUNICES 1 /* ... on MUNICes board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020018
19#ifndef CONFIG_SYS_TEXT_BASE
20#define CONFIG_SYS_TEXT_BASE 0xFFF00000
21#endif
22
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Becky Bruce31d82672008-05-08 19:02:12 -050025#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Heiko Schocher5fb2b232008-01-11 15:15:15 +010026
27/*
28 * Command line configuration.
29 */
30#include <config_cmd_default.h>
31
32#define CONFIG_CMD_ASKENV
33#define CONFIG_CMD_ELF
34#define CONFIG_CMD_IMMAP
35#define CONFIG_CMD_NET
36#define CONFIG_CMD_PING
37#define CONFIG_CMD_REGINFO
38
Jean-Christophe PLAGNIOL-VILLARD1b769882008-01-25 07:54:47 +010039#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schocher5fb2b232008-01-11 15:15:15 +010041#endif
42
43/*
44 * Serial console configuration
45 */
46#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schocher5fb2b232008-01-11 15:15:15 +010049
50#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52#undef CONFIG_BOOTARGS
53
54#define CONFIG_PREBOOT "echo;" \
55 "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
56 "echo"
57
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 "netdev=eth0\0" \
60 "nfsargs=setenv bootargs root=/dev/nfs rw " \
61 "nfsroot=$(serverip):$(rootpath)\0" \
62 "ramargs=setenv bootargs root=/dev/ram rw\0" \
63 "addip=setenv bootargs $(bootargs) " \
64 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
65 ":$(hostname):$(netdev):off panic=5\0" \
66 "flash_nfs=run nfsargs addip;" \
67 "bootm $(kernel_addr)\0" \
68 "flash_self=run ramargs addip;" \
69 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
70 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
71 "rootpath=/opt/eldk/ppc_6xx\0" \
72 "bootfile=/tftpboot/munices/u-boot.bin\0" \
73 "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \
74 "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \
75 ""
76#define CONFIG_BOOTCOMMAND "run net_nfs"
77
78/*
79 * IPB Bus clocking configuration.
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
82#if defined(CONFIG_SYS_IPBSPEED_133)
Heiko Schocher5fb2b232008-01-11 15:15:15 +010083/*
84 * PCI Bus clocking configuration
85 *
86 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
Heiko Schocher5fb2b232008-01-11 15:15:15 +010088 * been tested with a IPB Bus Clock of 66 MHz.
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */
Heiko Schocher5fb2b232008-01-11 15:15:15 +010091#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */
Heiko Schocher5fb2b232008-01-11 15:15:15 +010093#endif
94
95/*
96 * Memory map
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */
Heiko Schocherfa056642008-01-11 15:15:16 +010099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
101#define CONFIG_SYS_SDRAM_BASE 0x00000000
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100102/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200104#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200105#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100107
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200108#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
110# define CONFIG_SYS_RAMBOOT 1
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100111#endif
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
114#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
115#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100116
117/*
118 * Flash configuration
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_BASE 0xFF000000
121#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200122#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
124#define CONFIG_SYS_FLASH_EMPTY_INFO
125#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */
126#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
127#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100129
130/*
131 * Chip selects configuration
132 */
133/* Boot Chipselect */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
135#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
136#define CONFIG_SYS_BOOTCS_CFG 0x00047800
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100137
138/*
139 * Environment settings
140 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200141#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_OFFSET 0x40000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200143#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200144#define CONFIG_ENV_SECT_SIZE 0x20000
145#define CONFIG_ENV_SIZE 0x4000
146#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200147#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200148#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100149#define CONFIG_ENV_OVERWRITE 1
150
151/*
152 * Ethernet configuration
153 */
154#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800155#define CONFIG_MPC5xxx_FEC_MII100
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100156#define CONFIG_PHY_ADDR 0x01
157#define CONFIG_MII 1
158
159/*
160 * GPIO configuration
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100163 no PCI */
164
165/*
166 * Miscellaneous configurable options
167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_LONGHELP /* undef to save memory */
169#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
170#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
171#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
172#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
173#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
176#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
179#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100180
181#define CONFIG_DISPLAY_BOARDINFO 1
182#define CONFIG_CMDLINE_EDITING 1
183
184/*
185 * Various low-level settings
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
188#define CONFIG_SYS_HID0_FINAL HID0_ICE
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_CS_BURST 0x00000000
191#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
192#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Heiko Schocher5fb2b232008-01-11 15:15:15 +0100193
194/* pass open firmware flat tree */
195#define CONFIG_OF_LIBFDT 1
196#define CONFIG_OF_BOARD_SETUP 1
197
198#define OF_CPU "PowerPC,5200@0"
199#define OF_TBCLK (bd->bi_busfreq / 4)
200#define OF_SOC "soc5200@f0000000"
201#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
202
203#endif /* __CONFIG_H */