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Marek Vasutbc3a4a52010-04-05 01:50:57 +02001/*
2 * Aeronix Zipit Z2 configuration file
3 *
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Marek Vasutbc3a4a52010-04-05 01:50:57 +02007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010015#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
Marek Vasutbc3a4a52010-04-05 01:50:57 +020016#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
Marek Vasut9b3d1672010-10-20 22:02:16 +020017#define CONFIG_SYS_TEXT_BASE 0x0
Marek Vasutbc3a4a52010-04-05 01:50:57 +020018
Helmut Raiger9660e442011-10-20 04:19:47 +000019#undef CONFIG_BOARD_LATE_INIT
Marek Vasutbc3a4a52010-04-05 01:50:57 +020020#undef CONFIG_SKIP_LOWLEVEL_INIT
Marek Vasutaac316a2012-03-08 05:41:23 +000021#define CONFIG_PREBOOT
Marek Vasutbc3a4a52010-04-05 01:50:57 +020022
23/*
24 * Environment settings
25 */
26#define CONFIG_ENV_OVERWRITE
27#define CONFIG_ENV_IS_IN_FLASH 1
28#define CONFIG_ENV_ADDR 0x40000
29#define CONFIG_ENV_SIZE 0x20000
30
Simon Glass89959082012-10-30 13:38:53 +000031/* we will never enable dcache, because we have to setup MMU first */
32#define CONFIG_SYS_DCACHE_OFF
33
Marek Vasut24e84c32010-09-30 12:22:38 +020034#define CONFIG_SYS_MALLOC_LEN (128*1024)
Marek Vasut24e84c32010-09-30 12:22:38 +020035#define CONFIG_ARCH_CPU_INIT
Marek Vasutbc3a4a52010-04-05 01:50:57 +020036
37#define CONFIG_BOOTCOMMAND \
Vasily Khoruzhick81f731c2012-01-25 22:54:33 +030038 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
39 "then " \
Marek Vasutbc3a4a52010-04-05 01:50:57 +020040 "source 0xa0000000; " \
41 "else " \
42 "bootm 0x60000; " \
43 "fi; "
44#define CONFIG_BOOTARGS \
45 "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
46#define CONFIG_TIMESTAMP
47#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
48#define CONFIG_CMDLINE_TAG
49#define CONFIG_SETUP_MEMORY_TAGS
Marek Vasut24e84c32010-09-30 12:22:38 +020050#define CONFIG_SYS_TEXT_BASE 0x0
Marek Vasutbc3a4a52010-04-05 01:50:57 +020051#define CONFIG_LZMA /* LZMA compression support */
52
53/*
54 * Serial Console Configuration
55 * STUART - the lower serial port on Colibri board
56 */
57#define CONFIG_PXA_SERIAL
58#define CONFIG_STUART 1
Marek Vasutce6971c2012-09-12 12:36:25 +020059#define CONFIG_CONS_INDEX 2
Marek Vasutbc3a4a52010-04-05 01:50:57 +020060#define CONFIG_BAUDRATE 115200
Marek Vasutbc3a4a52010-04-05 01:50:57 +020061
62/*
63 * Bootloader Components Configuration
64 */
65#include <config_cmd_default.h>
66
67#undef CONFIG_CMD_NET
Sebastien Carlier6d8962e2010-11-05 15:48:07 +010068#undef CONFIG_CMD_NFS
Marek Vasutbc3a4a52010-04-05 01:50:57 +020069#define CONFIG_CMD_ENV
70#undef CONFIG_CMD_IMLS
71#define CONFIG_CMD_MMC
72#define CONFIG_CMD_SPI
73
74/*
75 * MMC Card Configuration
76 */
77#ifdef CONFIG_CMD_MMC
78#define CONFIG_MMC
Vasily Khoruzhick81f731c2012-01-25 22:54:33 +030079#define CONFIG_GENERIC_MMC
80#define CONFIG_PXA_MMC_GENERIC
Marek Vasutbc3a4a52010-04-05 01:50:57 +020081#define CONFIG_SYS_MMC_BASE 0xF0000000
82#define CONFIG_CMD_FAT
83#define CONFIG_CMD_EXT2
84#define CONFIG_DOS_PARTITION
85#endif
86
87/*
88 * SPI and LCD
89 */
90#ifdef CONFIG_CMD_SPI
91#define CONFIG_SOFT_SPI
92#define CONFIG_LCD
Jeroen Hofstee06980952013-01-22 10:44:10 +000093#define CONFIG_PXA_LCD
Marek Vasutbc3a4a52010-04-05 01:50:57 +020094#define CONFIG_LMS283GF05
95#define CONFIG_VIDEO_LOGO
96#define CONFIG_CMD_BMP
97#define CONFIG_SPLASH_SCREEN
98#define CONFIG_SPLASH_SCREEN_ALIGN
99#define CONFIG_VIDEO_BMP_GZIP
100#define CONFIG_VIDEO_BMP_RLE8
101#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
102#undef SPI_INIT
103
104#define SPI_DELAY udelay(10)
105#define SPI_SDA(val) zipitz2_spi_sda(val)
106#define SPI_SCL(val) zipitz2_spi_scl(val)
107#define SPI_READ zipitz2_spi_read()
108#ifndef __ASSEMBLY__
109void zipitz2_spi_sda(int);
110void zipitz2_spi_scl(int);
111unsigned char zipitz2_spi_read(void);
112#endif
113#endif
114
115/*
116 * KGDB
117 */
118#ifdef CONFIG_CMD_KGDB
119#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
120#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
121#endif
122
123/*
124 * HUSH Shell Configuration
125 */
126#define CONFIG_SYS_HUSH_PARSER 1
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200127
128#define CONFIG_SYS_LONGHELP /* undef to save memory */
129#ifdef CONFIG_SYS_HUSH_PARSER
130#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
131#else
132#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
133#endif
134#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
135#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
136#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
137#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
138#define CONFIG_SYS_DEVICE_NULLDEV 1
139
140/*
141 * Clock Configuration
142 */
143#undef CONFIG_SYS_CLKS_IN_HZ
144#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
145#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
146
147/*
Vasily Khoruzhick76d4ae22012-01-13 10:11:44 +0300148 * SRAM Map
149 */
150#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
151#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
152
153/*
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200154 * DRAM Map
155 */
156#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
157#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
158#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
159
160#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
161#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
162
163#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
164#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
165
166#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
167
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200168#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Vasily Khoruzhick76d4ae22012-01-13 10:11:44 +0300169#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200170
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200171/*
172 * NOR FLASH
173 */
174#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
175#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
176#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
177#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
178
179#define CONFIG_SYS_FLASH_CFI
180#define CONFIG_FLASH_CFI_DRIVER 1
181#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
182
183#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
184#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
185
186#define CONFIG_SYS_MAX_FLASH_BANKS 1
187#define CONFIG_SYS_MAX_FLASH_SECT 256
188
189#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
190
191#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
192#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
193#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
194#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
195#define CONFIG_SYS_FLASH_PROTECTION
196
197/*
198 * GPIO settings
199 */
200#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
201#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
202#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
203#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
204#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
205#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
206#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
207#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
208#define CONFIG_SYS_GPCR0_VAL 0x00000000
209#define CONFIG_SYS_GPCR1_VAL 0x00000020
210#define CONFIG_SYS_GPCR2_VAL 0x00000000
211#define CONFIG_SYS_GPCR3_VAL 0x00000000
212#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
213#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
Marek Vasut24e84c32010-09-30 12:22:38 +0200214#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200215#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
216#define CONFIG_SYS_GPSR0_VAL 0x06080400
217#define CONFIG_SYS_GPSR1_VAL 0x007f0000
218#define CONFIG_SYS_GPSR2_VAL 0x032a0000
219#define CONFIG_SYS_GPSR3_VAL 0x00000180
220
221#define CONFIG_SYS_PSSR_VAL 0x30
222
223/*
224 * Clock settings
225 */
226#define CONFIG_SYS_CKEN 0x00511220
227#define CONFIG_SYS_CCCR 0x00000190
228
229/*
230 * Memory settings
231 */
232#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
233#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
234#define CONFIG_SYS_MSC2_VAL 0x0000b884
235#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
236#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
237#define CONFIG_SYS_MDMRS_VAL 0x00000000
238#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
239#define CONFIG_SYS_SXCNFG_VAL 0x40044004
240
241/*
242 * PCMCIA and CF Interfaces
243 */
244#define CONFIG_SYS_MECR_VAL 0x00000001
245#define CONFIG_SYS_MCMEM0_VAL 0x00014307
246#define CONFIG_SYS_MCMEM1_VAL 0x00014307
247#define CONFIG_SYS_MCATT0_VAL 0x0001c787
248#define CONFIG_SYS_MCATT1_VAL 0x0001c787
249#define CONFIG_SYS_MCIO0_VAL 0x0001430f
250#define CONFIG_SYS_MCIO1_VAL 0x0001430f
251
252#endif /* __CONFIG_H */