| Fabio Estevam | 2f9b07d | 2023-08-08 18:40:38 -0300 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT |
| 2 | |
| Fabio Estevam | 45651a3 | 2023-09-12 12:11:00 -0300 | [diff] [blame] | 3 | #include "imx7s-u-boot.dtsi" |
| 4 | |
| Joris Offouga | 0d52bab | 2019-12-08 18:02:30 +0100 | [diff] [blame] | 5 | &fec2 { |
| 6 | status = "disable"; |
| 7 | }; |
| Joris Offouga | 41fe56e | 2020-01-29 22:06:01 +0100 | [diff] [blame] | 8 | |
| 9 | &usbotg1 { |
| 10 | dr_mode = "peripheral"; |
| 11 | }; |
| Fabio Estevam | 0aea5dd | 2023-04-12 09:41:04 -0300 | [diff] [blame] | 12 | |
| 13 | &usdhc1 { |
| 14 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 15 | pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; |
| 16 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; |
| 17 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; |
| 18 | }; |
| 19 | |
| 20 | &pinctrl_usdhc1 { |
| 21 | fsl,pins = < |
| 22 | MX7D_PAD_SD1_CMD__SD1_CMD 0x59 |
| 23 | MX7D_PAD_SD1_CLK__SD1_CLK 0x19 |
| 24 | MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 |
| 25 | MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 |
| 26 | MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 |
| 27 | MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 |
| 28 | >; |
| 29 | }; |
| 30 | |
| 31 | &iomuxc { |
| 32 | pinctrl_usdhc1_gpio: usdhc1gpiogrp { |
| 33 | fsl,pins = < |
| 34 | MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ |
| 35 | MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ |
| 36 | MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ |
| 37 | MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ |
| 38 | >; |
| 39 | }; |
| 40 | |
| 41 | pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { |
| 42 | fsl,pins = < |
| 43 | MX7D_PAD_SD1_CMD__SD1_CMD 0x5a |
| 44 | MX7D_PAD_SD1_CLK__SD1_CLK 0x1a |
| 45 | MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a |
| 46 | MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a |
| 47 | MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a |
| 48 | MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a |
| 49 | >; |
| 50 | }; |
| 51 | |
| 52 | pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { |
| 53 | fsl,pins = < |
| 54 | MX7D_PAD_SD1_CMD__SD1_CMD 0x5b |
| 55 | MX7D_PAD_SD1_CLK__SD1_CLK 0x1b |
| 56 | MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b |
| 57 | MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b |
| 58 | MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b |
| 59 | MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b |
| 60 | >; |
| 61 | }; |
| 62 | }; |