Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * K3: ARM64 MMU setup |
| 4 | * |
| 5 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | * Lokesh Vutla <lokeshvutla@ti.com> |
| 7 | * (This file is derived from arch/arm/cpu/armv8/zynqmp/cpu.c) |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <asm/system.h> |
| 13 | #include <asm/armv8/mmu.h> |
| 14 | |
| 15 | /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ |
| 16 | #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) |
| 17 | |
| 18 | /* ToDo: Add 64bit IO */ |
| 19 | struct mm_region am654_mem_map[NR_MMU_REGIONS] = { |
| 20 | { |
| 21 | .virt = 0x0UL, |
| 22 | .phys = 0x0UL, |
| 23 | .size = 0x80000000UL, |
| 24 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 25 | PTE_BLOCK_NON_SHARE | |
| 26 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 27 | }, { |
| 28 | .virt = 0x80000000UL, |
| 29 | .phys = 0x80000000UL, |
| 30 | .size = 0x80000000UL, |
| 31 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 32 | PTE_BLOCK_INNER_SHARE |
| 33 | }, { |
| 34 | .virt = 0x880000000UL, |
| 35 | .phys = 0x880000000UL, |
| 36 | .size = 0x80000000UL, |
| 37 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 38 | PTE_BLOCK_INNER_SHARE |
| 39 | }, { |
| 40 | /* List terminator */ |
| 41 | 0, |
| 42 | } |
| 43 | }; |
| 44 | |
| 45 | struct mm_region *mem_map = am654_mem_map; |