blob: 2d88c7ce770a4608476db9e3ae66f459346a22e8 [file] [log] [blame]
Macpaul Lin4bed7262011-05-01 21:28:56 +00001/*
2 * Faraday FTIDE020_s ATA Controller (AHB)
3 *
4 * (C) Copyright 2011 Andes Technology
5 * Greentime Hu <greentime@andestech.com>
6 * Macpaul Lin <macpaul@andestech.com>
7 * Kuo-Wei Chou <kwchou@andestech.com>
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Macpaul Lin4bed7262011-05-01 21:28:56 +000010 */
11
12#ifndef __FTIDE020_H
13#define __FTIDE020_H
14
15/* ftide020.h - ide support functions for the FTIDE020_S controller */
16
17/* ATA controller register offset */
18struct ftide020_s {
19 unsigned int rw_fifo; /* 0x00 - READ/WRITE FIFO */
20 unsigned int cmd_fifo; /* 0x04 - R: Status Reg, W: CMD_FIFO */
21 unsigned int cr; /* 0x08 - Control Reg */
22 unsigned int dmatirr; /* 0x0c - DMA Threshold/Interrupt Reg */
23 unsigned int ctrd0; /* 0x10 - Command Timing Reg Device 0 */
24 unsigned int dtrd0; /* 0x14 - Data Timing Reg Device 0 */
25 unsigned int ctrd1; /* 0x18 - Command Timing Reg Device 1 */
26 unsigned int dtrd1; /* 0x1c - Data Timing Reg Device 1 */
27 unsigned int ahbtr; /* 0x20 - AHB Timeout Reg */
28 unsigned int RESVD0; /* 0x24 */
29 unsigned int RESVD1; /* 0x28 */
30 unsigned int RESVD2; /* 0x2c */
31 unsigned int f_cfifo; /* 0x30 - Feature Info of CMD_FIFO */
32 unsigned int f_wfifo; /* 0x34 - Feature Info of WRITE_FIFO */
33 unsigned int f_rfifo; /* 0x3c - Feature Info of READ_FIFO */
34 unsigned int revision; /* 0x38 - Revision No. of FTIDE020_S */
35};
36
37/* reference parameters */
38#define CONFIG_IDE_REG_CS 0x2 /* ref: ATA spec chaper 10, table 42 */
39#define CONFIG_CTRD1_PROBE_T1 0x2
40#define CONFIG_CTRD1_PROBE_T2 0x5
41
42/* status register - 0x04 */
43#define STATUS_CSEL (1 << 0) /* CSEL */
44#define STATUS_CS(x) (((x) >> 1) & 0x3) /* CS#[1:0] */
45#define STATUS_DMACK (1 << 3) /* DMACK# */
46#define STATUS_DMARQ (1 << 4) /* DMA req */
47#define STATUS_INTRQ (1 << 5) /* INT req */
48#define STATUS_DIOR (1 << 6) /* DIOR */
49#define STATUS_IORDY (1 << 7) /* I/O ready */
50#define STATUS_DIOW (1 << 8) /* DIOW# */
51#define STATUS_PDIAG (1 << 9) /* PDIAG */
52#define STATUS_DASP (1 << 10) /* DASP# */
53#define STATUS_DEV (1 << 11) /* selected device */
54#define STATUS_PIO (1 << 12) /* PIO in progress */
55#define STATUS_DMA (1 << 13) /* DMA in progress */
56#define STATUS_WFE (1 << 14) /* write fifo full */
57#define STATUS_RFE (1 << 15) /* read fifo empty */
58#define STATUS_COUNTER(x) (((x) >> 16) & 0x3fff) /* data tx counter */
59#define STATUS_ERR (1 << 30) /* trasfer terminated */
60#define STATUS_AER (1 << 31) /* AHB timeout indicate */
61
62/* Control register - 0x08 */
63#define CONTROL_TYPE_PIO 0x0
64#define CONTROL_TYPE_UDMA 0x1
65
66/* Device 0 */
67#define CONTROL_TYP0(x) (((x) & 0x7) << 0)
68#define CONTROL_IRE0 (1 << 3) /* enable IORDY for PIO */
69#define CONTROL_RESVD_DW0 (1 << 4) /* Reserved - DW0 ? */
70#define CONTROL_E0 (1 << 5) /* E0: 1: Big Endian */
71#define CONTROL_RESVD_WP0 (1 << 6) /* Reserved - WP0 ? */
72#define CONTROL_RESVD_SE0 (1 << 7) /* Reserved - SE0 ? */
73#define CONTROL_RESVD_ECC0 (1 << 8) /* Reserved - ECC0 ? */
74
75#define CONTROL_RAEIE (1 << 9) /* IRQ - read fifo almost full */
76#define CONTROL_RNEIE (1 << 10) /* IRQ - read fifo not empty */
77#define CONTROL_WAFIE (1 << 11) /* IRQ - write fifo almost empty */
78#define CONTROL_WNFIE (1 << 12) /* IRQ - write fifo not full */
79#define CONTROL_RESVD_FIRQ (1 << 13) /* RESERVED - FIRQ ? */
80#define CONTROL_AERIE (1 << 14) /* IRQ - AHB timeout error */
81#define CONTROL_IIE (1 << 15) /* IDE IRQ enable */
82
83/* Device 1 */
84#define CONTROL_TYP1(x) (((x) & 0x7) << 16)
85#define CONTROL_IRE1 (1 << 19) /* enable IORDY for PIO */
86#define CONTROL_RESVD_DW1 (1 << 20) /* Reserved - DW1 ? */
87#define CONTROL_E1 (1 << 21) /* E1: 1: Big Endian */
88#define CONTROL_RESVD_WP1 (1 << 22) /* Reserved - WP1 ? */
89#define CONTROL_RESVD_SE1 (1 << 23) /* Reserved - SE1 ? */
90#define CONTROL_RESVD_ECC1 (1 << 24) /* Reserved - ECC1 ? */
91
92#define CONTROL_DRE (1 << 25) /* DMA receive enable */
93#define CONTROL_DTE (1 << 26) /* DMA transmit enable */
94#define CONTRIL_RESVD (1 << 27)
95#define CONTROL_TERIE (1 << 28) /* transfer terminate error IRQ */
96#define CONTROL_T (1 << 29) /* terminate current operation */
97#define CONTROL_SRST (1 << 30) /* IDE soft reset */
98#define CONTROL_RST (1 << 31) /* IDE hardware reset */
99
100/* IRQ register - 0x0c */
101#define IRQ_RXTHRESH(x) (((x) & 0x3ff) << 0) /* Read FIFO threshold */
102#define IRQ_RFAEIRQ (1 << 10) /* Read FIFO almost full intr req */
103#define IRQ_RFNEIRQ (1 << 11) /* Read FIFO not empty intr req */
104#define IRQ_WFAFIRQ (1 << 12) /* Write FIFO almost empty int req */
105#define IRQ_WFNFIRQ (1 << 13) /* Write FIFO not full intr req */
106#define IRQ_RESVD_FIRQ (1 << 14) /* Reserved - FIRQ ? */
107#define IRQ_IIRQ (1 << 15) /* IDE device interrupt request */
108#define IRQ_TXTHRESH(x) (((x) & 0x3ff) << 16) /* Write FIFO thershold */
109#define IRQ_TERMERR (1 << 28) /* Transfer termination indication */
110#define IRQ_AHBERR (1 << 29) /* AHB Timeout indication */
111
112/* Command Timing Register 0-1: ctrd (0x10, 0x18) */
113#define CT_REG_T1(x) (((x) & 0xff) << 0) /* setup time of addressed */
114#define CT_REG_T2(x) (((x) & 0xff) << 8) /* pluse width of DIOR/DIOW */
115#define CT_REG_T4(x) (((x) & 0xff) << 16) /* data hold time */
116#define CT_REG_TEOC(x) (((x) & 0xff) << 24) /* time to the end of a cycle */
117
118/* Data Timing Register 0-1: dtrd (0x14, 0x1c) */
119/*
120 * PIO mode:
121 * b(0:7) DT_REG_PIO_T1: the setup time of addressed
122 * b(8:15) DT_REG_PIO_T2: the pluse width of DIOR/DIOW
123 * b(16:23) DT_REG_PIO_T4: data hold time
124 * b(24:31) DT_REG_PIO_TEOC: the time to the end of a cycle
125 */
126#define DT_REG_PIO_T1(x) (((x) & 0xff) << 0)
127#define DT_REG_PIO_T2(x) (((x) & 0xff) << 8)
128#define DT_REG_PIO_T4(x) (((x) & 0xff) << 16)
129#define DT_REG_PIO_TEOC(x) (((x) & 0xff) << 24)
130
131/*
132 * UDMA mode:
133 * b(0:3) DT_REG_UDMA_TENV: the envelope time
134 * b(4:7) DT_REG_UDMA_TMLI: interlock time
135 * b(8:15) DT_REG_UDMA_TCYC: cycle time - data time
136 * b(16:19) DT_REG_UDMA_TACK: setup and hold time of DMACK
137 * b(23:30) DT_REG_UDMA_TCVS: setup time of CRC
138 * b(24:31) DT_REG_UDMA_TRP: time to ready to pause
139 */
140#define DT_REG_UDMA_TENV(x) (((x) & 0xf) << 0)
141#define DT_REG_UDMA_TMLI(x) (((x) & 0xf) << 4)
142#define DT_REG_UDMA_TCYC(x) (((x) & 0xff) << 8)
143#define DT_REG_UDMA_TACK(x) (((x) & 0xf) << 16)
144#define DT_REG_UDMA_TCVS(x) (((x) & 0xf) << 20)
145#define DT_REG_UDMA_TRP(x) (((x) & 0xff) << 24)
146
147/* ftide020_s command formats */
148/* read: IDE Register (CF1) */
149#define IDE_REG_OPCODE_READ (1 << 13) /* 0x2000 */
150#define IDE_REG_CS_READ(x) (((x) & 0x3) << 11)
151#define IDE_REG_DA_READ(x) (((x) & 0x7) << 8)
152#define IDE_REG_CMD_READ(x) 0x0 /* fixed value */
153
154/* write: IDE Register (CF2) */
155#define IDE_REG_OPCODE_WRITE (0x5 << 13) /* 0xA000 */
156#define IDE_REG_CS_WRITE(x) (((x) & 0x3) << 11)
157#define IDE_REG_DA_WRITE(x) (((x) & 0x7) << 8)
158/* b(0:7) IDE_REG_CMD_WRITE(x): Actual ATA command or data */
159#define IDE_REG_CMD_WRITE(x) (((x) & 0xff) << 0)
160
161/* read/write data: PIO/UDMA (CF3) */
162#define IDE_DATA_WRITE (1 << 15) /* read: 0, write: 1 */
163#define IDE_DATA_OPCODE (0x2 << 13) /* device data access opcode */
164/* b(0:12) IDE_DATA_COUNTER(x): Number of transfers minus 1 */
165#define IDE_DATA_COUNTER(x) (((x) & 0x1fff) << 0)
166
167/* set device: (CF4) */
168#define IDE_SET_OPCODE (0x2740 << 2) /* [15:2], 0x9d00 */
169/* CF3 counter value: 0: Tx in bytes, 1: in blocks (each block is 8 bytes) */
170#define IDE_SET_CX8(x) (((x) & 0x1) << 1)
171#define IDE_SET_DEV(x) (((x) & 0x1) << 0) /* 0: Master, 1: Slave */
172
173/*
174 * IDE command bit definition
175 * This section is designed for minor hardware revision compatibility.
176 */
177#define READ_REG_CMD IDE_REG_OPCODE_READ /* 0x2000 */
178#define WRITE_REG_CMD IDE_REG_OPCODE_WRITE /* 0xA000 */
179#define READ_DATA_CMD IDE_DATA_OPCODE /* 0x4000 */
180#define WRITE_DATA_CMD (IDE_DATA_OPCODE | IDE_DATA_WRITE) /* 0xC000 */
181#define SET_DEV_CMD IDE_SET_OPCODE /* 0x9D00 */
182
183#define TATOL_TIMING 3
184#define CMD_TIMING 0
185#define PIO_TIMING 1
186#define DMA_TIMING 2
187
188/* Timing Parameters */
189/* Register Access Timing Parameters */
190#define REG_PARAMETER 4
191#define REG_T0 0
192#define REG_T1 1
193#define REG_T2 2
194#define REG_T4 3
195
196#define REG_MODE 5
197#define REG_MODE0 0
198#define REG_MODE1 1
199#define REG_MODE2 2
200#define REG_MODE3 3
201#define REG_MODE4 4
202
203/* PIO Access Timing Parameters */
204#define PIO_PARAMETER 4
205#define PIO_T0 0
206#define PIO_T1 1
207#define PIO_T2 2
208#define PIO_T4 3
209
210#define PIO_MODE 5
211#define PIO_MODE0 0
212#define PIO_MODE1 1
213#define PIO_MODE2 2
214#define PIO_MODE3 3
215#define PIO_MODE4 4
216
217/* UDMA Access Timing Parameters */
218#define UDMA_PARAMETER 6
219#define UDMA_TCYC 0
220#define UDMA_TCVS 1
221#define UDMA_TMLI 2
222#define UDMA_TENV 3
223#define UDMA_TRP 4
224#define UDMA_TACK 5
225
226#define UDMA_MODE 7
227#define UDMA_MODE0 0
228#define UDMA_MODE1 1
229#define UDMA_MODE2 2
230#define UDMA_MODE3 3
231#define UDMA_MODE4 4
232#define UDMA_MODE5 5
233#define UDMA_MODE6 6
234
235/*
236 * RX_THRESH:
237 * hardware limitation: max = 8, should support 1,4,8,16,32,64,128,256
238 */
239#define RX_THRESH 8
240#define WRITE_FIFO 32 /* Hardwired value */
241
242/* Time Table */
243unsigned int REG_ACCESS_TIMING[REG_PARAMETER][REG_MODE] = {
244 {600, 383, 330, 180, 120},
245 {70, 50, 30, 30, 25},
246 {290, 290, 290, 80, 70},
247 {30, 20, 15, 10, 10},
248};
249
250unsigned int PIO_ACCESS_TIMING[PIO_PARAMETER][PIO_MODE] = {
251 {600, 383, 240, 180, 120},
252 {70, 50, 30, 30, 25},
253 {165, 125, 100, 80, 70},
254 {30, 20, 15, 10, 10},
255};
256
257unsigned int UDMA_ACCESS_TIMING[UDMA_PARAMETER][UDMA_MODE] = {
258 {1120, 730, 540, 390, 250, 168, 130}, /* 10X */
259 {700, 480, 310, 200, 67, 100, 100}, /* 10X */
260 {200, 200, 200, 200, 200, 200, 200}, /* 10X */
261 {200, 200, 200, 200, 200, 200, 200}, /* 10X */
262 {1600, 1250, 1000, 1000, 1000, 850, 850}, /* 10X */
263 {200, 200, 200, 200, 200, 200, 200}, /* 10X */
264};
265
266#endif /* __FTIDE020_H */