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Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
2 * U-boot - Configuration file for BF533 STAMP board
3 */
4
5#ifndef __CONFIG_STAMP_H__
6#define __CONFIG_STAMP_H__
7
8#define CONFIG_STAMP 1
9#define CONFIG_RTC_BFIN 1
10#define CONFIG_BF533 1
11/*
12 * Boot Mode Set
13 * Blackfin can support several boot modes
14 */
Aubrey Li8db13d62007-03-10 23:49:29 +080015#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
16#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
17#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
Aubrey.Li3f0606a2007-03-09 13:38:44 +080018/* Define the boot mode */
19#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
Aubrey Li8db13d62007-03-10 23:49:29 +080020/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
Aubrey.Li3f0606a2007-03-09 13:38:44 +080021
22#define CONFIG_PANIC_HANG 1
23
24#define ADSP_BF531 0x31
25#define ADSP_BF532 0x32
26#define ADSP_BF533 0x33
27#define BFIN_CPU ADSP_BF533
28
29/* This sets the default state of the cache on U-Boot's boot */
30#define CONFIG_ICACHE_ON
31#define CONFIG_DCACHE_ON
32
33/* Define where the uboot will be loaded by on-chip boot rom */
34#define APP_ENTRY 0x00001000
35
36/*
37 * Stringize definitions - needed for environmental settings
38 */
39#define STRINGIZE2(x) #x
40#define STRINGIZE(x) STRINGIZE2(x)
41
42/*
43 * Board settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080044 */
Aubrey Li8db13d62007-03-10 23:49:29 +080045#define CONFIG_DRIVER_SMC91111 1
46#define CONFIG_SMC91111_BASE 0x20300300
Aubrey.Li3f0606a2007-03-09 13:38:44 +080047
48/* FLASH/ETHERNET uses the same address range */
Aubrey Li8db13d62007-03-10 23:49:29 +080049#define SHARED_RESOURCES 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +080050
51/* Is I2C bit-banged? */
Aubrey Li8db13d62007-03-10 23:49:29 +080052#define CONFIG_SOFT_I2C 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +080053
54/*
55 * Software (bit-bang) I2C driver configuration
56 */
Aubrey Li8db13d62007-03-10 23:49:29 +080057#define PF_SCL PF3
58#define PF_SDA PF2
Aubrey.Li3f0606a2007-03-09 13:38:44 +080059
60/*
61 * Video splash screen support
62 */
Aubrey Li8db13d62007-03-10 23:49:29 +080063#define CONFIG_VIDEO 0
Aubrey.Li3f0606a2007-03-09 13:38:44 +080064
Aubrey Li8db13d62007-03-10 23:49:29 +080065#define CONFIG_VDSP 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +080066
67/*
68 * Clock settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080069 */
70
Aubrey Li8db13d62007-03-10 23:49:29 +080071/* CONFIG_CLKIN_HZ is any value in Hz */
72#define CONFIG_CLKIN_HZ 11059200
73/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
74/* 1=CLKIN/2 */
75#define CONFIG_CLKIN_HALF 0
76/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
77/* 1=bypass PLL */
78#define CONFIG_PLL_BYPASS 0
79/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
80/* Values can range from 1-64 */
81#define CONFIG_VCO_MULT 36
82/* CONFIG_CCLK_DIV controls what the core clock divider is */
83/* Values can be 1, 2, 4, or 8 ONLY */
84#define CONFIG_CCLK_DIV 1
85/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
86/* Values can range from 1-15 */
87#define CONFIG_SCLK_DIV 5
88/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
89/* Values can range from 2-65535 */
90/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
91#define CONFIG_SPI_BAUD 2
Aubrey.Li3f0606a2007-03-09 13:38:44 +080092
93#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +080094#define CONFIG_SPI_BAUD_INITBLOCK 4
Aubrey.Li3f0606a2007-03-09 13:38:44 +080095#endif
96
Aubrey.Li3f0606a2007-03-09 13:38:44 +080097/*
98 * Network settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080099 */
100
101#if (CONFIG_DRIVER_SMC91111)
102#if 0
103#define CONFIG_MII
104#endif
105
106/* network support */
Aubrey Li8db13d62007-03-10 23:49:29 +0800107#define CONFIG_IPADDR 192.168.0.15
108#define CONFIG_NETMASK 255.255.255.0
109#define CONFIG_GATEWAYIP 192.168.0.1
110#define CONFIG_SERVERIP 192.168.0.2
111#define CONFIG_HOSTNAME STAMP
112#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800113
114/* To remove hardcoding and enable MAC storage in EEPROM */
Aubrey Li8db13d62007-03-10 23:49:29 +0800115/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800116#endif /* CONFIG_DRIVER_SMC91111 */
117
118/*
119 * Flash settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800120 */
121
Aubrey Li8db13d62007-03-10 23:49:29 +0800122#define CFG_FLASH_CFI /* The flash is CFI compatible */
Aubrey Li0d93de12007-03-12 12:11:55 +0800123#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800124#define CFG_FLASH_CFI_AMD_RESET
125
Aubrey Li8db13d62007-03-10 23:49:29 +0800126#define CFG_FLASH_BASE 0x20000000
127#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
128#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800129
130#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +0800131#define CFG_ENV_IS_IN_FLASH 1
132#define CFG_ENV_ADDR 0x20004000
133#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800134#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +0800135#define CFG_ENV_IS_IN_EEPROM 1
136#define CFG_ENV_OFFSET 0x4000
137#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800138#endif
139
Aubrey Li8db13d62007-03-10 23:49:29 +0800140#define CFG_ENV_SIZE 0x2000
141#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800142#define ENV_IS_EMBEDDED
143
Aubrey Li8db13d62007-03-10 23:49:29 +0800144#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800145#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
Aubrey Li8db13d62007-03-10 23:49:29 +0800146#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800147
148/* JFFS Partition offset set */
149#define CFG_JFFS2_FIRST_BANK 0
150#define CFG_JFFS2_NUM_BANKS 1
151/* 512k reserved for u-boot */
Aubrey Li8db13d62007-03-10 23:49:29 +0800152#define CFG_JFFS2_FIRST_SECTOR 11
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800153
154/*
155 * following timeouts shall be used once the
156 * Flash real protection is enabled
157 */
Aubrey Li8db13d62007-03-10 23:49:29 +0800158#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
159#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800160
161/*
162 * SDRAM settings & memory map
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800163 */
164
Aubrey Li8db13d62007-03-10 23:49:29 +0800165#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
166#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800167#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
168
169#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +0800170#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800171#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +0800172#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800173#endif
174
Aubrey Li8db13d62007-03-10 23:49:29 +0800175#define CFG_SDRAM_BASE 0x00000000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800176
177#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
178#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
179#define CONFIG_LOADADDR 0x01000000
180
Aubrey Li8db13d62007-03-10 23:49:29 +0800181#define CFG_LOAD_ADDR CONFIG_LOADADDR
182#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
183#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
184#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
185#define CONFIG_STACKSIZE (128*1024) /* regular stack */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800186
187#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
Aubrey Li8db13d62007-03-10 23:49:29 +0800188#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
189#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
190#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800191
192/* Check to make sure everything fits in SDRAM */
193#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
194 #error Memory Map does not fit into configuration
195#endif
196
197#if ( CONFIG_CLKIN_HALF == 0 )
Aubrey Li8db13d62007-03-10 23:49:29 +0800198#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800199#else
Aubrey Li8db13d62007-03-10 23:49:29 +0800200#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800201#endif
202
203#if (CONFIG_PLL_BYPASS == 0)
Aubrey Li8db13d62007-03-10 23:49:29 +0800204#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
205#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800206#else
Aubrey Li8db13d62007-03-10 23:49:29 +0800207#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
208#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800209#endif
210
211#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
212#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
213#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
214#else
215#undef CONFIG_SPI_FLASH_FAST_READ
216#endif
217#endif
Aubrey Li8db13d62007-03-10 23:49:29 +0800218
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800219/*
220 * Command settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800221 */
222
Aubrey Li8db13d62007-03-10 23:49:29 +0800223#define CFG_LONGHELP 1
224#define CONFIG_CMDLINE_EDITING 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800225
226#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +0800227#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800228#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800229
Aubrey Li8db13d62007-03-10 23:49:29 +0800230/* configuration lookup from the BOOTP/DHCP server, */
Aubrey Li0d93de12007-03-12 12:11:55 +0800231/* but not try to load any image using TFTP */
Aubrey Li8db13d62007-03-10 23:49:29 +0800232
233#define CONFIG_BOOTDELAY 5
234#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800235#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +0800236#define CONFIG_BOOTCOMMAND "run ramboot"
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800237#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
Aubrey Li8db13d62007-03-10 23:49:29 +0800238#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800239#endif
240
Aubrey Li8db13d62007-03-10 23:49:29 +0800241#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800242
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800243
244#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
245#if (CONFIG_DRIVER_SMC91111)
246#define CONFIG_EXTRA_ENV_SETTINGS \
Aubrey Li8db13d62007-03-10 23:49:29 +0800247 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
248 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
249 "$(rootpath) console=ttyBF0,57600\0" \
250 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
251 "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
252 "ramboot=tftpboot $(loadaddr) linux; " \
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800253 "run ramargs;run addip;bootelf\0" \
Aubrey Li8db13d62007-03-10 23:49:29 +0800254 "nfsboot=tftpboot $(loadaddr) linux; " \
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800255 "run nfsargs;run addip;bootelf\0" \
Aubrey Li8db13d62007-03-10 23:49:29 +0800256 "flashboot=bootm 0x20100000\0" \
257 "update=tftpboot $(loadaddr) u-boot.bin; " \
258 "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
259 "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
260 ""
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800261#else
262#define CONFIG_EXTRA_ENV_SETTINGS \
Aubrey Li8db13d62007-03-10 23:49:29 +0800263 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
264 "flashboot=bootm 0x20100000\0" \
265 "
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800266#endif
267
268#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
269#define CONFIG_EXTRA_ENV_SETTINGS \
270 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
271 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
272 "$(rootpath) console=ttyBF0,57600\0" \
273 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
274 "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
Aubrey Li0d93de12007-03-12 12:11:55 +0800275 "ramboot=tftpboot $(loadaddr) linux; " \
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800276 "run ramargs;run addip;bootelf\0" \
277 "nfsboot=tftpboot $(loadaddr) linux; " \
278 "run nfsargs;run addip;bootelf\0" \
279 "flashboot=bootm 0x20100000\0" \
280 "update=tftpboot $(loadaddr) u-boot.ldr;" \
281 "eeprom write $(loadaddr) 0x0 $(filesize);\0"\
282 ""
283#endif
284
285#ifdef CONFIG_SOFT_I2C
286#if (!CONFIG_SOFT_I2C)
287#undef CONFIG_SOFT_I2C
288#endif
289#endif
290
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800291
Jon Loeligerba2351f2007-07-04 22:31:49 -0500292/*
293 * Command line configuration.
294 */
295#include <config_cmd_default.h>
296
297#define CONFIG_CMD_ELF
298#define CONFIG_CMD_CACHE
299#define CONFIG_CMD_JFFS2
300#define CONFIG_CMD_EEPROM
301#define CONFIG_CMD_DATE
302
303#if (CONFIG_DRIVER_SMC91111)
304#define CONFIG_CMD_PING
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800305#endif
306
Jon Loeligerba2351f2007-07-04 22:31:49 -0500307#if (CONFIG_SOFT_I2C)
308#define CONFIG_CMD_I2C
309#endif
310
311#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
312#define CONFIG_CMD_DHCP
313#endif
314
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800315
316/*
317 * Console settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800318 */
319
Aubrey Li8db13d62007-03-10 23:49:29 +0800320#define CONFIG_BAUDRATE 57600
321#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800322
323#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
324#if (BFIN_CPU == ADSP_BF531)
Aubrey Li8db13d62007-03-10 23:49:29 +0800325#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800326#elif (BFIN_CPU == ADSP_BF532)
Aubrey Li8db13d62007-03-10 23:49:29 +0800327#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800328#else
Aubrey Li8db13d62007-03-10 23:49:29 +0800329#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800330#endif
331#else
332#if (BFIN_CPU == ADSP_BF531)
Aubrey Li8db13d62007-03-10 23:49:29 +0800333#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800334#elif (BFIN_CPU == ADSP_BF532)
Aubrey Li8db13d62007-03-10 23:49:29 +0800335#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800336#else
Aubrey Li8db13d62007-03-10 23:49:29 +0800337#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800338#endif
339#endif
340
Jon Loeligerba2351f2007-07-04 22:31:49 -0500341#if defined(CONFIG_CMD_KGDB)
Aubrey Li8db13d62007-03-10 23:49:29 +0800342#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800343#else
Aubrey Li8db13d62007-03-10 23:49:29 +0800344#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800345#endif
Aubrey Li8db13d62007-03-10 23:49:29 +0800346#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
347#define CFG_MAXARGS 16 /* max number of command args */
348#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800349
Aubrey Li8db13d62007-03-10 23:49:29 +0800350#define CONFIG_LOADS_ECHO 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800351
352/*
353 * I2C settings
354 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
355 */
356#if (CONFIG_SOFT_I2C)
357
Aubrey Li8db13d62007-03-10 23:49:29 +0800358#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
359#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
360#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
361#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
362#define I2C_SDA(bit) if(bit) { \
363 *pFIO_FLAG_S = PF_SDA; \
364 asm("ssync;"); \
365 } \
366 else { \
367 *pFIO_FLAG_C = PF_SDA; \
368 asm("ssync;"); \
369 }
370#define I2C_SCL(bit) if(bit) { \
371 *pFIO_FLAG_S = PF_SCL; \
372 asm("ssync;"); \
373 } \
374 else { \
375 *pFIO_FLAG_C = PF_SCL; \
376 asm("ssync;"); \
377 }
378#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800379
Aubrey Li8db13d62007-03-10 23:49:29 +0800380#define CFG_I2C_SPEED 50000
381#define CFG_I2C_SLAVE 0xFE
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800382#endif /* CONFIG_SOFT_I2C */
383
384/*
385 * Compact Flash settings
386 */
387
388/* Enabled below option for CF support */
Aubrey Li8db13d62007-03-10 23:49:29 +0800389/* #define CONFIG_STAMP_CF 1 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800390
Jon Loeligerba2351f2007-07-04 22:31:49 -0500391#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800392
Aubrey Li8db13d62007-03-10 23:49:29 +0800393#define CONFIG_MISC_INIT_R 1
394#define CONFIG_DOS_PARTITION 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800395/*
396 * IDE/ATA stuff
397 */
Aubrey Li8db13d62007-03-10 23:49:29 +0800398#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
399#undef CONFIG_IDE_LED /* no led for ide supported */
400#undef CONFIG_IDE_RESET /* no reset for ide supported */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800401
Aubrey Li8db13d62007-03-10 23:49:29 +0800402#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
403#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800404
Aubrey Li8db13d62007-03-10 23:49:29 +0800405#define CFG_ATA_BASE_ADDR 0x20200000
406#define CFG_ATA_IDE0_OFFSET 0x0000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800407
Aubrey Li8db13d62007-03-10 23:49:29 +0800408#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
409#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
410#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800411
Aubrey Li8db13d62007-03-10 23:49:29 +0800412#define CFG_ATA_STRIDE 2
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800413#endif
414
415/*
416 * Miscellaneous configurable options
417 */
418
Aubrey Li8db13d62007-03-10 23:49:29 +0800419#define CFG_HZ 1000 /* 1ms time tick */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800420
Aubrey Li8db13d62007-03-10 23:49:29 +0800421#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800422
Aubrey Li8db13d62007-03-10 23:49:29 +0800423#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800424
425#define CONFIG_SPI
426
427#ifdef CONFIG_VIDEO
428#if (CONFIG_VIDEO)
Aubrey Li8db13d62007-03-10 23:49:29 +0800429#define CONFIG_SPLASH_SCREEN 1
430#define CONFIG_SILENT_CONSOLE 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800431#else
432#undef CONFIG_VIDEO
433#endif
434#endif
435
436/*
437 * FLASH organization and environment definitions
438 */
Aubrey Li8db13d62007-03-10 23:49:29 +0800439#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800440
441/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
Aubrey Li8db13d62007-03-10 23:49:29 +0800442/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
443#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
444 B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
445#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
446 B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800447*/
Aubrey Li8db13d62007-03-10 23:49:29 +0800448#define AMGCTLVAL 0xFF
449#define AMBCTL0VAL 0xBBC3BBC3
450#define AMBCTL1VAL 0x99B39983
451#define CF_AMBCTL1VAL 0x99B3ffc2
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800452
453#ifdef CONFIG_VDSP
454#define ET_EXEC_VDSP 0x8
455#define SHT_STRTAB_VDSP 0x1
456#define ELFSHDRSIZE_VDSP 0x2C
457#define VDSP_ENTRY_ADDR 0xFFA00000
458#endif
459
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800460#endif