blob: 1dd53e2313f31b278e52f814f492914758b3def1 [file] [log] [blame]
Beniamino Galvanibfcef282016-05-08 08:30:16 +02001/*
2 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <libfdt.h>
9#include <linux/err.h>
10#include <asm/arch/gxbb.h>
Beniamino Galvanic7757d42016-05-08 08:30:17 +020011#include <asm/arch/sm.h>
Beniamino Galvanibfcef282016-05-08 08:30:16 +020012#include <asm/armv8/mmu.h>
13#include <asm/unaligned.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17int dram_init(void)
18{
19 const fdt64_t *val;
20 int offset;
21 int len;
22
23 offset = fdt_path_offset(gd->fdt_blob, "/memory");
24 if (offset < 0)
25 return -EINVAL;
26
27 val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
28 if (len < sizeof(*val) * 2)
29 return -EINVAL;
30
31 /* Use unaligned access since cache is still disabled */
32 gd->ram_size = get_unaligned_be64(&val[1]);
33
34 return 0;
35}
36
37void dram_init_banksize(void)
38{
39 /* Reserve first 16 MiB of RAM for firmware */
40 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
41 gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
42}
43
44void reset_cpu(ulong addr)
45{
46 psci_system_reset(true);
47}
48
49static struct mm_region gxbb_mem_map[] = {
50 {
York Suncd4b0c52016-06-24 16:46:22 -070051 .virt = 0x0UL,
52 .phys = 0x0UL,
Beniamino Galvanibfcef282016-05-08 08:30:16 +020053 .size = 0x80000000UL,
54 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
55 PTE_BLOCK_INNER_SHARE
56 }, {
York Suncd4b0c52016-06-24 16:46:22 -070057 .virt = 0x80000000UL,
58 .phys = 0x80000000UL,
Beniamino Galvanibfcef282016-05-08 08:30:16 +020059 .size = 0x80000000UL,
60 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
61 PTE_BLOCK_NON_SHARE |
62 PTE_BLOCK_PXN | PTE_BLOCK_UXN
63 }, {
64 /* List terminator */
65 0,
66 }
67};
68
69struct mm_region *mem_map = gxbb_mem_map;