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wdenk384cc682005-04-03 22:35:21 +00001 /*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28#include <common.h>
29#include <pci.h>
Ben Warrenad3381c2008-08-31 10:44:19 -070030#include <netdev.h>
wdenk384cc682005-04-03 22:35:21 +000031#include <asm/processor.h>
Kumar Galad53bd3e2008-08-26 23:51:49 -050032#include <asm/mmu.h>
wdenk384cc682005-04-03 22:35:21 +000033#include <asm/immap_85xx.h>
Kumar Galad53bd3e2008-08-26 23:51:49 -050034#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060035#include <spd_sdram.h>
wdenk384cc682005-04-03 22:35:21 +000036
37#if defined(CONFIG_DDR_ECC)
38extern void ddr_enable_ecc(unsigned int dram_size);
39#endif
40
wdenk384cc682005-04-03 22:35:21 +000041void local_bus_init(void);
42void sdram_init(void);
43long int fixed_sdram(void);
44
45
46int board_early_init_f (void)
47{
48#if defined(CONFIG_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
wdenk384cc682005-04-03 22:35:21 +000050
51 pci->peer &= 0xffffffdf; /* disable master abort */
52#endif
53
54 return 0;
55}
56
57int checkboard (void)
58{
59 puts("Board: MicroSys PM854\n");
60
61#ifdef CONFIG_PCI
62 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
63 CONFIG_SYS_CLK_FREQ / 1000000);
64#else
65 printf(" PCI1: disabled\n");
66#endif
67
68 /*
69 * Initialize local bus.
70 */
71 local_bus_init();
72
73 return 0;
74}
75
76
Becky Bruce9973e3c2008-06-09 16:03:40 -050077phys_size_t
wdenk384cc682005-04-03 22:35:21 +000078initdram(int board_type)
79{
80 long dram_size = 0;
wdenk384cc682005-04-03 22:35:21 +000081
82 puts("Initializing\n");
83
84#if defined(CONFIG_DDR_DLL)
85 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
wdenk384cc682005-04-03 22:35:21 +000087 int i,x;
wdenk8b0bfc62005-04-03 23:11:38 +000088
wdenk384cc682005-04-03 22:35:21 +000089 x = 10;
wdenk8b0bfc62005-04-03 23:11:38 +000090
wdenk384cc682005-04-03 22:35:21 +000091 /*
92 * Work around to stabilize DDR DLL
93 */
94 gur->ddrdllcr = 0x81000000;
95 asm("sync;isync;msync");
96 udelay (200);
97 while (gur->ddrdllcr != 0x81000100)
98 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020099 gur->devdisr = gur->devdisr | 0x00010000;
wdenk384cc682005-04-03 22:35:21 +0000100 asm("sync;isync;msync");
101 for (i=0; i<x; i++)
102 ;
103 gur->devdisr = gur->devdisr & 0xfff7ffff;
104 asm("sync;isync;msync");
105 x++;
106 }
wdenk8b0bfc62005-04-03 23:11:38 +0000107 }
wdenk384cc682005-04-03 22:35:21 +0000108#endif
109
110#if defined(CONFIG_SPD_EEPROM)
Kumar Galad53bd3e2008-08-26 23:51:49 -0500111 dram_size = fsl_ddr_sdram();
112 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
113 dram_size *= 0x100000;
wdenk384cc682005-04-03 22:35:21 +0000114#else
115 dram_size = fixed_sdram ();
116#endif
117
118#if defined(CONFIG_DDR_ECC)
119 /*
120 * Initialize and enable DDR ECC.
121 */
122 ddr_enable_ecc(dram_size);
123#endif
124 puts(" DDR: ");
125 return dram_size;
126}
127
128
129/*
130 * Initialize Local Bus
131 */
132
133void
134local_bus_init(void)
135{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500137 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
wdenk384cc682005-04-03 22:35:21 +0000138
139 uint clkdiv;
140 uint lbc_hz;
141 sys_info_t sysinfo;
142
143 /*
144 * Errata LBC11.
145 * Fix Local Bus clock glitch when DLL is enabled.
146 *
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200147 * If localbus freq is < 66MHz, DLL bypass mode must be used.
148 * If localbus freq is > 133MHz, DLL can be safely enabled.
wdenk384cc682005-04-03 22:35:21 +0000149 * Between 66 and 133, the DLL is enabled with an override workaround.
150 */
151
152 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800153 clkdiv = lbc->lcrr & LCRR_CLKDIV;
wdenk384cc682005-04-03 22:35:21 +0000154 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
155
156 if (lbc_hz < 66) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
wdenk384cc682005-04-03 22:35:21 +0000158
159 } else if (lbc_hz >= 133) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
wdenk384cc682005-04-03 22:35:21 +0000161
162 } else {
163 /*
164 * On REV1 boards, need to change CLKDIV before enable DLL.
165 * Default CLKDIV is 8, change it to 4 temporarily.
166 */
167 uint pvr = get_pvr();
168 uint temp_lbcdll = 0;
169
170 if (pvr == PVR_85xx_REV1) {
171 /* FIXME: Justify the high bit here. */
172 lbc->lcrr = 0x10000004;
173 }
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
wdenk384cc682005-04-03 22:35:21 +0000176 udelay(200);
177
178 /*
179 * Sample LBC DLL ctrl reg, upshift it to set the
180 * override bits.
181 */
182 temp_lbcdll = gur->lbcdllcr;
183 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
184 asm("sync;isync;msync");
185 }
186}
187
188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#if defined(CONFIG_SYS_DRAM_TEST)
wdenk384cc682005-04-03 22:35:21 +0000190int testdram (void)
191{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
193 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
wdenk384cc682005-04-03 22:35:21 +0000194 uint *p;
195
196 printf("SDRAM test phase 1:\n");
197 for (p = pstart; p < pend; p++)
198 *p = 0xaaaaaaaa;
199
200 for (p = pstart; p < pend; p++) {
201 if (*p != 0xaaaaaaaa) {
202 printf ("SDRAM test fails at: %08x\n", (uint) p);
203 return 1;
204 }
205 }
206
207 printf("SDRAM test phase 2:\n");
208 for (p = pstart; p < pend; p++)
209 *p = 0x55555555;
210
211 for (p = pstart; p < pend; p++) {
212 if (*p != 0x55555555) {
213 printf ("SDRAM test fails at: %08x\n", (uint) p);
214 return 1;
215 }
216 }
217
218 printf("SDRAM test passed.\n");
219 return 0;
220}
221#endif
222
223
224#if !defined(CONFIG_SPD_EEPROM)
225/*************************************************************************
226 * fixed sdram init -- doesn't use serial presence detect.
227 ************************************************************************/
228long int fixed_sdram (void)
229{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230 #ifndef CONFIG_SYS_RAMBOOT
231 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
wdenk384cc682005-04-03 22:35:21 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
234 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
235 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
236 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
237 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
238 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
wdenk384cc682005-04-03 22:35:21 +0000239 #if defined (CONFIG_DDR_ECC)
240 ddr->err_disable = 0x0000000D;
241 ddr->err_sbe = 0x00ff0000;
242 #endif
243 asm("sync;isync;msync");
244 udelay(500);
245 #if defined (CONFIG_DDR_ECC)
246 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
wdenk384cc682005-04-03 22:35:21 +0000248 #else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
wdenk384cc682005-04-03 22:35:21 +0000250 #endif
251 asm("sync; isync; msync");
252 udelay(500);
253 #endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
wdenk384cc682005-04-03 22:35:21 +0000255}
256#endif /* !defined(CONFIG_SPD_EEPROM) */
257
258
259#if defined(CONFIG_PCI)
260/*
261 * Initialize PCI Devices, report devices found.
262 */
263
264#ifndef CONFIG_PCI_PNP
265static struct pci_config_table pci_pm854_config_table[] = {
266 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_IDSEL_NUMBER, PCI_ANY_ID,
268 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
269 PCI_ENET0_MEMADDR,
270 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
271 } },
272 { }
273};
274#endif
275
276
277static struct pci_controller hose = {
278#ifndef CONFIG_PCI_PNP
279 config_table: pci_pm854_config_table,
280#endif
281};
282
283#endif /* CONFIG_PCI */
284
285
286void
287pci_init_board(void)
288{
289#ifdef CONFIG_PCI
wdenk384cc682005-04-03 22:35:21 +0000290 pci_mpc85xx_init(&hose);
291#endif /* CONFIG_PCI */
292}
Ben Warrenad3381c2008-08-31 10:44:19 -0700293
294int board_eth_init(bd_t *bis)
295{
Ben Warren10efa022008-08-31 20:37:00 -0700296 cpu_eth_init(bis); /* Intialize TSECs first */
Ben Warrenad3381c2008-08-31 10:44:19 -0700297 return pci_eth_init(bis);
298}