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wdenk9dd41a72005-05-12 22:48:09 +00001/*
2 * (C) Copyright 2005
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37#define CONFIG_MPC8272_FAMILY 1
38#define CONFIG_IDS8247 1
39#define CPU_ID_STR "MPC8247"
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050040#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk9dd41a72005-05-12 22:48:09 +000041
42#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
43
44#define CONFIG_BOOTCOUNT_LIMIT
45
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010046#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk9dd41a72005-05-12 22:48:09 +000047
48#undef CONFIG_BOOTARGS
49
50#define CONFIG_EXTRA_ENV_SETTINGS \
51 "netdev=eth0\0" \
52 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "nfsroot=${serverip}:${rootpath}\0" \
wdenk9dd41a72005-05-12 22:48:09 +000054 "ramargs=setenv bootargs root=/dev/ram rw " \
55 "console=ttyS0,115200\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010056 "addip=setenv bootargs ${bootargs} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
58 ":${hostname}:${netdev}:off panic=1\0" \
wdenk9dd41a72005-05-12 22:48:09 +000059 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "bootm ${kernel_addr}\0" \
wdenk9dd41a72005-05-12 22:48:09 +000061 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
63 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk9dd41a72005-05-12 22:48:09 +000064 "rootpath=/opt/eldk/ppc_82xx\0" \
65 "bootfile=/tftpboot/IDS8247/uImage\0" \
66 "kernel_addr=ff800000\0" \
67 "ramdisk_addr=ffa00000\0" \
68 ""
69#define CONFIG_BOOTCOMMAND "run flash_self"
70
71#define CONFIG_MISC_INIT_R 1
72
73/* enable I2C and select the hardware/software driver */
74#undef CONFIG_HARD_I2C /* I2C with hardware support */
75#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
77#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk9dd41a72005-05-12 22:48:09 +000078
79/*
80 * Software (bit-bang) I2C driver configuration
81 */
82
83#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
84#define I2C_ACTIVE (iop->pdir |= 0x00000080)
85#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
86#define I2C_READ ((iop->pdat & 0x00000080) != 0)
87#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
88 else iop->pdat &= ~0x00000080
89#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
90 else iop->pdat &= ~0x00000100
91#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
92
93#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
95#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
96#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
97#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk9dd41a72005-05-12 22:48:09 +000098
99#define CONFIG_I2C_X
100#endif
101
102/*
103 * select serial console configuration
104 * use the extern UART for the console
105 */
106#define CONFIG_CONS_INDEX 1
107#define CONFIG_BAUDRATE 115200
108/*
109 * NS16550 Configuration
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_NS16550
112#define CONFIG_SYS_NS16550_SERIAL
wdenk9dd41a72005-05-12 22:48:09 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk9dd41a72005-05-12 22:48:09 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_NS16550_CLK 14745600
wdenk9dd41a72005-05-12 22:48:09 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_UART_BASE 0xE0000000
119#define CONFIG_SYS_UART_SIZE 0x10000
wdenk9dd41a72005-05-12 22:48:09 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
wdenk9dd41a72005-05-12 22:48:09 +0000122
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200123
124/* pass open firmware flat tree */
125#define CONFIG_OF_LIBFDT 1
126#define CONFIG_OF_BOARD_SETUP 1
127
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200128#define OF_TBCLK (bd->bi_busfreq / 4)
129#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
130
131
wdenk9dd41a72005-05-12 22:48:09 +0000132/*
133 * select ethernet configuration
134 *
135 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
136 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
137 * for FCC)
138 *
139 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500140 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk9dd41a72005-05-12 22:48:09 +0000141 */
142#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
143#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
144#undef CONFIG_ETHER_NONE /* define if ether on something else */
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200145#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
146#define CONFIG_ETHER_ON_FCC1
147#define FCC_ENET
wdenk9dd41a72005-05-12 22:48:09 +0000148
149/*
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200150 * - Rx-CLK is CLK10
151 * - Tx-CLK is CLK9
wdenk9dd41a72005-05-12 22:48:09 +0000152 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
153 * - Enable Full Duplex in FSMR
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
156# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
157# define CONFIG_SYS_CPMFCR_RAMTYPE 0
158# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk9dd41a72005-05-12 22:48:09 +0000159
160
161/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
162#define CONFIG_8260_CLKIN 66666666 /* in Hz */
163
164#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk9dd41a72005-05-12 22:48:09 +0000166
167#undef CONFIG_WATCHDOG /* watchdog disabled */
168
169#define CONFIG_TIMESTAMP /* Print image info with timestamp */
170
Jon Loeliger7be044e2007-07-09 21:24:19 -0500171/*
172 * BOOTP options
173 */
174#define CONFIG_BOOTP_SUBNETMASK
175#define CONFIG_BOOTP_GATEWAY
176#define CONFIG_BOOTP_HOSTNAME
177#define CONFIG_BOOTP_BOOTPATH
178#define CONFIG_BOOTP_BOOTFILESIZE
wdenk9dd41a72005-05-12 22:48:09 +0000179
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200180#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk9dd41a72005-05-12 22:48:09 +0000182
Jon Loeliger348f2582007-07-08 13:46:18 -0500183/*
184 * Command line configuration.
185 */
186#include <config_cmd_default.h>
187
188#define CONFIG_CMD_DHCP
189#define CONFIG_CMD_NFS
190#define CONFIG_CMD_NAND
191#define CONFIG_CMD_I2C
192#define CONFIG_CMD_SNTP
193
wdenk9dd41a72005-05-12 22:48:09 +0000194
195/*
196 * Miscellaneous configurable options
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_LONGHELP /* undef to save memory */
199#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500200#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk9dd41a72005-05-12 22:48:09 +0000202#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk9dd41a72005-05-12 22:48:09 +0000204#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
206#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
207#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk9dd41a72005-05-12 22:48:09 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
210#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk9dd41a72005-05-12 22:48:09 +0000211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk9dd41a72005-05-12 22:48:09 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk9dd41a72005-05-12 22:48:09 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk9dd41a72005-05-12 22:48:09 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
wdenk9dd41a72005-05-12 22:48:09 +0000219
220/*
221 * For booting Linux, the board info and command line data
222 * have to be in the first 8 MB of memory, since this is
223 * the maximum mapped by the Linux kernel during initialization.
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk9dd41a72005-05-12 22:48:09 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200228#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
230#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
wdenk9dd41a72005-05-12 22:48:09 +0000231/* What should the base address of the main FLASH be and how big is
232 * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
233 * The main FLASH is whichever is connected to *CS0.
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
236#define CONFIG_SYS_FLASH0_SIZE 8
wdenk9dd41a72005-05-12 22:48:09 +0000237
238/* Flash bank size (for preliminary settings)
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
wdenk9dd41a72005-05-12 22:48:09 +0000241
242/*-----------------------------------------------------------------------
243 * FLASH organization
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
246#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk9dd41a72005-05-12 22:48:09 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
249#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk9dd41a72005-05-12 22:48:09 +0000250
251/* Environment in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200252#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200254#define CONFIG_ENV_SIZE 0x20000
255#define CONFIG_ENV_SECT_SIZE 0x20000
wdenk9dd41a72005-05-12 22:48:09 +0000256
257/*-----------------------------------------------------------------------
258 * NAND-FLASH stuff
259 *-----------------------------------------------------------------------
260 */
Jon Loeliger348f2582007-07-08 13:46:18 -0500261#if defined(CONFIG_CMD_NAND)
wdenk9dd41a72005-05-12 22:48:09 +0000262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_NAND0_BASE 0xE1000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
wdenk9dd41a72005-05-12 22:48:09 +0000265
Jon Loeliger11799432007-07-10 09:02:57 -0500266#endif /* CONFIG_CMD_NAND */
wdenk9dd41a72005-05-12 22:48:09 +0000267
268/*-----------------------------------------------------------------------
269 * Hard Reset Configuration Words
270 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk9dd41a72005-05-12 22:48:09 +0000272 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk9dd41a72005-05-12 22:48:09 +0000274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
wdenk9dd41a72005-05-12 22:48:09 +0000276
277/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_HRCW_SLAVE1 0
279#define CONFIG_SYS_HRCW_SLAVE2 0
280#define CONFIG_SYS_HRCW_SLAVE3 0
281#define CONFIG_SYS_HRCW_SLAVE4 0
282#define CONFIG_SYS_HRCW_SLAVE5 0
283#define CONFIG_SYS_HRCW_SLAVE6 0
284#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk9dd41a72005-05-12 22:48:09 +0000285
286/*-----------------------------------------------------------------------
287 * Internal Memory Mapped Register
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_IMMR 0xF0000000
wdenk9dd41a72005-05-12 22:48:09 +0000290
291/*-----------------------------------------------------------------------
292 * Definitions for initial stack pointer and data area (in DPRAM)
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
295#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
296#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
297#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
298#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk9dd41a72005-05-12 22:48:09 +0000299
300/*-----------------------------------------------------------------------
301 * Start addresses for the final memory configuration
302 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk9dd41a72005-05-12 22:48:09 +0000304 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
wdenk9dd41a72005-05-12 22:48:09 +0000306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_SDRAM_BASE 0x00000000
308#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
309#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
310#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
311#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk9dd41a72005-05-12 22:48:09 +0000312
313/*
314 * Internal Definitions
315 *
316 * Boot Flags
317 */
318#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
319#define BOOTFLAG_WARM 0x02 /* Software reboot */
320
321
322/*-----------------------------------------------------------------------
323 * Cache Configuration
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger348f2582007-07-08 13:46:18 -0500326#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk9dd41a72005-05-12 22:48:09 +0000328#endif
329
330/*-----------------------------------------------------------------------
331 * HIDx - Hardware Implementation-dependent Registers 2-11
332 *-----------------------------------------------------------------------
333 * HID0 also contains cache control - initially enable both caches and
334 * invalidate contents, then the final state leaves only the instruction
335 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
336 * but Soft reset does not.
337 *
338 * HID1 has only read-only information - nothing to set.
339 */
340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
342#define CONFIG_SYS_HID0_FINAL 0
343#define CONFIG_SYS_HID2 0
wdenk9dd41a72005-05-12 22:48:09 +0000344
345/*-----------------------------------------------------------------------
346 * RMR - Reset Mode Register 5-5
347 *-----------------------------------------------------------------------
348 * turn on Checkstop Reset Enable
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_RMR 0
wdenk9dd41a72005-05-12 22:48:09 +0000351
352/*-----------------------------------------------------------------------
353 * BCR - Bus Configuration 4-25
354 *-----------------------------------------------------------------------
355 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_BCR 0
wdenk9dd41a72005-05-12 22:48:09 +0000357
358/*-----------------------------------------------------------------------
359 * SIUMCR - SIU Module Configuration 4-31
360 *-----------------------------------------------------------------------
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
wdenk9dd41a72005-05-12 22:48:09 +0000363
364/*-----------------------------------------------------------------------
365 * SYPCR - System Protection Control 4-35
366 * SYPCR can only be written once after reset!
367 *-----------------------------------------------------------------------
368 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
369 */
370#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk9dd41a72005-05-12 22:48:09 +0000372 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
373#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk9dd41a72005-05-12 22:48:09 +0000375 SYPCR_SWRI|SYPCR_SWP)
376#endif /* CONFIG_WATCHDOG */
377
378/*-----------------------------------------------------------------------
379 * TMCNTSC - Time Counter Status and Control 4-40
380 *-----------------------------------------------------------------------
381 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
382 * and enable Time Counter
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk9dd41a72005-05-12 22:48:09 +0000385
386/*-----------------------------------------------------------------------
387 * PISCR - Periodic Interrupt Status and Control 4-42
388 *-----------------------------------------------------------------------
389 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
390 * Periodic timer
391 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk9dd41a72005-05-12 22:48:09 +0000393
394/*-----------------------------------------------------------------------
395 * SCCR - System Clock Control 9-8
396 *-----------------------------------------------------------------------
397 * Ensure DFBRG is Divide by 16
398 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
wdenk9dd41a72005-05-12 22:48:09 +0000400
401/*-----------------------------------------------------------------------
402 * RCCR - RISC Controller Configuration 13-7
403 *-----------------------------------------------------------------------
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_RCCR 0
wdenk9dd41a72005-05-12 22:48:09 +0000406
407/*
408 * Init Memory Controller:
409 *
410 * Bank Bus Machine PortSz Device
411 * ---- --- ------- ------ ------
412 * 0 60x GPCM 16 bit FLASH
413 * 1 60x GPCM 8 bit NAND
414 * 2 60x SDRAM 32 bit SDRAM
415 * 3 60x GPCM 8 bit UART
416 *
417 */
418
419#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
420
421/* Minimum mask to separate preliminary
422 * address ranges for CS[0:2]
423 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
wdenk9dd41a72005-05-12 22:48:09 +0000425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_MPTPR 0x6600
wdenk9dd41a72005-05-12 22:48:09 +0000427
428/*-----------------------------------------------------------------------------
429 * Address for Mode Register Set (MRS) command
430 *-----------------------------------------------------------------------------
431 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_MRS_OFFS 0x00000110
wdenk9dd41a72005-05-12 22:48:09 +0000433
434
435/* Bank 0 - FLASH
436 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk9dd41a72005-05-12 22:48:09 +0000438 BRx_PS_8 |\
439 BRx_MS_GPCM_P |\
440 BRx_V)
441
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk9dd41a72005-05-12 22:48:09 +0000443 ORxG_SCY_6_CLK )
444
Jon Loeliger348f2582007-07-08 13:46:18 -0500445#if defined(CONFIG_CMD_NAND)
wdenk9dd41a72005-05-12 22:48:09 +0000446/* Bank 1 - NAND Flash
447*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
449#define CONFIG_SYS_NAND_SIZE 0x8000
wdenk9dd41a72005-05-12 22:48:09 +0000450
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_OR_TIMING_NAND 0x000036
wdenk9dd41a72005-05-12 22:48:09 +0000452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
454#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
wdenk9dd41a72005-05-12 22:48:09 +0000455#endif
456
457/* Bank 2 - 60x bus SDRAM
458 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_PSRT 0x20
460#define CONFIG_SYS_LSRT 0x20
wdenk9dd41a72005-05-12 22:48:09 +0000461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenk9dd41a72005-05-12 22:48:09 +0000463 BRx_PS_32 |\
464 BRx_MS_SDRAM_P |\
465 BRx_V)
466
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
wdenk9dd41a72005-05-12 22:48:09 +0000468
469
470/* SDRAM initialization values
471*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk9dd41a72005-05-12 22:48:09 +0000473 ORxS_BPD_4 |\
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200474 ORxS_ROWST_PBI0_A9 |\
wdenk9dd41a72005-05-12 22:48:09 +0000475 ORxS_NUMR_12)
476
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
wdenk9dd41a72005-05-12 22:48:09 +0000478 PSDMR_BSMA_A15_A17 |\
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200479 PSDMR_SDA10_PBI0_A10 |\
wdenk9dd41a72005-05-12 22:48:09 +0000480 PSDMR_RFRC_5_CLK |\
481 PSDMR_PRETOACT_2W |\
482 PSDMR_ACTTORW_2W |\
483 PSDMR_BL |\
484 PSDMR_LDOTOPRE_2C |\
485 PSDMR_WRC_3C |\
486 PSDMR_CL_3)
487
488/* Bank 3 - UART
489*/
490
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
492#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
wdenk9dd41a72005-05-12 22:48:09 +0000493
494#endif /* __CONFIG_H */