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Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040013#include <asm/sizes.h>
14
15/*
16 * High Level Configuration Options
17 */
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040018#define CONFIG_OMAP 1 /* in a TI OMAP core */
19#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Marek Vasut308252a2012-07-21 05:02:23 +000020#define CONFIG_OMAP_GPIO
Lokesh Vutla806d2792013-07-30 11:36:30 +053021#define CONFIG_OMAP_COMMON
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040022
23#define CONFIG_SDRC /* The chip has SDRC controller */
24
25#include <asm/arch/cpu.h>
26#include <asm/arch/omap3.h>
Enric Balletbo i Serraaa127df2013-02-07 00:40:05 +000027#include <asm/mach-types.h>
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040028
29/*
30 * Display CPU and Board information
31 */
32#define CONFIG_DISPLAY_CPUINFO 1
33#define CONFIG_DISPLAY_BOARDINFO 1
34
35/* Clock Defines */
36#define V_OSCK 26000000 /* Clock output from T2 */
37#define V_SCLK (V_OSCK >> 1)
38
39#define CONFIG_MISC_INIT_R
40
41#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42#define CONFIG_SETUP_MEMORY_TAGS 1
43#define CONFIG_INITRD_TAG 1
44#define CONFIG_REVISION_TAG 1
45
Enric Balletbo i Serrae284f882013-03-15 02:32:35 +000046#define CONFIG_OF_LIBFDT
47#define CONFIG_CMD_BOOTZ
Javier Martinez Canillas372d7fa2013-08-11 18:20:00 +020048#define CONFIG_SUPPORT_RAW_INITRD
Grant Likely2fa8ca92011-03-28 09:59:07 +000049
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040050/*
51 * NS16550 Configuration
52 */
53
54#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
55
56#define CONFIG_SYS_NS16550
57#define CONFIG_SYS_NS16550_SERIAL
58#define CONFIG_SYS_NS16550_REG_SIZE (-4)
59#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
60
61/* select serial console configuration */
62#define CONFIG_CONS_INDEX 3
63#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
64#define CONFIG_SERIAL3 3
65
66/* allow to overwrite serial and ethaddr */
67#define CONFIG_ENV_OVERWRITE
68#define CONFIG_BAUDRATE 115200
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +000069#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
70 115200}
Enric Balletbo i Serraf49d7b62010-11-04 15:34:33 -040071#define CONFIG_GENERIC_MMC 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040072#define CONFIG_MMC 1
Enric Balletbo i Serraf49d7b62010-11-04 15:34:33 -040073#define CONFIG_OMAP_HSMMC 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040074#define CONFIG_DOS_PARTITION 1
75
Javier Martinez Canillas9d4f5422012-12-27 03:36:01 +000076/* define to enable boot progress via leds */
Enric Balletbo i Serrad9aacf42013-02-07 00:40:06 +000077#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
78 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
Javier Martinez Canillas9d4f5422012-12-27 03:36:01 +000079#define CONFIG_SHOW_BOOT_PROGRESS
Enric Balletbo i Serrad9aacf42013-02-07 00:40:06 +000080#endif
Javier Martinez Canillas9d4f5422012-12-27 03:36:01 +000081
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040082/* USB */
83#define CONFIG_MUSB_UDC 1
84#define CONFIG_USB_OMAP3 1
85#define CONFIG_TWL4030_USB 1
86
87/* USB device configuration */
88#define CONFIG_USB_DEVICE 1
89#define CONFIG_USB_TTY 1
90#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
91
92/* Change these to suit your needs */
93#define CONFIG_USBD_VENDORID 0x0451
94#define CONFIG_USBD_PRODUCTID 0x5678
95#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
96#define CONFIG_USBD_PRODUCT_NAME "IGEP"
97
98/* commands to include */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_CACHE
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200102#define CONFIG_CMD_EXT4
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400103#define CONFIG_CMD_FAT /* FAT support */
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200104#define CONFIG_CMD_FS_GENERIC
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400105#define CONFIG_CMD_I2C /* I2C serial bus support */
106#define CONFIG_CMD_MMC /* MMC support */
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000107#ifdef CONFIG_BOOT_ONENAND
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400108#define CONFIG_CMD_ONENAND /* ONENAND support */
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000109#endif
110#ifdef CONFIG_BOOT_NAND
111#define CONFIG_CMD_NAND
112#endif
Enric Balletbo i Serrad9aacf42013-02-07 00:40:06 +0000113#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
114 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400115#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
Javier Martinez Canillas77eea282012-12-27 01:35:56 +0000116#endif
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400117#define CONFIG_CMD_DHCP
118#define CONFIG_CMD_PING
119#define CONFIG_CMD_NFS /* NFS support */
120#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
121#define CONFIG_MTD_DEVICE
122
123#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
124#undef CONFIG_CMD_IMLS /* List all found images */
125
126#define CONFIG_SYS_NO_FLASH
127#define CONFIG_HARD_I2C 1
128#define CONFIG_SYS_I2C_SPEED 100000
129#define CONFIG_SYS_I2C_SLAVE 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400130#define CONFIG_DRIVER_OMAP34XX_I2C 1
131
132/*
133 * TWL4030
134 */
135#define CONFIG_TWL4030_POWER 1
136
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400137#define CONFIG_BOOTDELAY 3
138
139#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400140 "usbtty=cdc_acm\0" \
141 "loadaddr=0x82000000\0" \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +0200142 "dtbaddr=0x81600000\0" \
143 "bootdir=/boot\0" \
144 "bootfile=zImage\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400145 "usbtty=cdc_acm\0" \
Javier Martinez Canillase5e73c12012-06-29 02:45:40 +0000146 "console=ttyO2,115200n8\0" \
Enric Balletbo i Serraf1e445c2012-04-25 02:34:31 +0000147 "mpurate=auto\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400148 "vram=12M\0" \
149 "dvimode=1024x768MR-16@60\0" \
150 "defaultdisplay=dvi\0" \
151 "mmcdev=0\0" \
152 "mmcroot=/dev/mmcblk0p2 rw\0" \
Javier Martinez Canillasb4ebeb82012-06-29 02:45:41 +0000153 "mmcrootfstype=ext4 rootwait\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400154 "nandroot=/dev/mtdblock4 rw\0" \
155 "nandrootfstype=jffs2\0" \
156 "mmcargs=setenv bootargs console=${console} " \
157 "mpurate=${mpurate} " \
158 "vram=${vram} " \
159 "omapfb.mode=dvi:${dvimode} " \
160 "omapfb.debug=y " \
161 "omapdss.def_disp=${defaultdisplay} " \
162 "root=${mmcroot} " \
163 "rootfstype=${mmcrootfstype}\0" \
164 "nandargs=setenv bootargs console=${console} " \
165 "mpurate=${mpurate} " \
166 "vram=${vram} " \
167 "omapfb.mode=dvi:${dvimode} " \
168 "omapfb.debug=y " \
169 "omapdss.def_disp=${defaultdisplay} " \
170 "root=${nandroot} " \
171 "rootfstype=${nandrootfstype}\0" \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200172 "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
Enric Balletbo i Serra1b8ec012012-04-25 02:33:50 +0000173 "importbootenv=echo Importing environment from mmc ...; " \
174 "env import -t $loadaddr $filesize\0" \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +0200175 "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
176 "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400177 "mmcboot=echo Booting from mmc ...; " \
178 "run mmcargs; " \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200179 "bootz ${loadaddr}\0" \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +0200180 "mmcbootfdt=echo Booting with DT from mmc ...; " \
181 "bootz ${loadaddr} - ${dtbaddr}\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400182 "nandboot=echo Booting from onenand ...; " \
183 "run nandargs; " \
184 "onenand read ${loadaddr} 280000 400000; " \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200185 "bootz ${loadaddr}\0" \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400186
187#define CONFIG_BOOTCOMMAND \
Andrew Bradford66968112012-10-01 05:06:52 +0000188 "mmc dev ${mmcdev}; if mmc rescan; then " \
Enric Balletbo i Serra1b8ec012012-04-25 02:33:50 +0000189 "echo SD/MMC found on device ${mmcdev};" \
190 "if run loadbootenv; then " \
191 "run importbootenv;" \
192 "fi;" \
193 "if test -n $uenvcmd; then " \
194 "echo Running uenvcmd ...;" \
195 "run uenvcmd;" \
196 "fi;" \
Enric Balletbo i Serra2be6bed2013-08-07 17:53:18 +0200197 "if run loadzimage; then " \
Javier Martinez Canillasa2fa28b2013-08-07 17:53:19 +0200198 "if test -n $dtbfile; then " \
199 "if run loadfdt; then " \
200 "run mmcbootfdt;" \
201 "fi;" \
202 "fi;" \
Enric Balletbo i Serra1b8ec012012-04-25 02:33:50 +0000203 "run mmcboot;" \
204 "fi;" \
205 "fi;" \
206 "run nandboot;" \
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400207
208#define CONFIG_AUTO_COMPLETE 1
209
210/*
211 * Miscellaneous configurable options
212 */
213#define CONFIG_SYS_LONGHELP /* undef to save memory */
214#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400215#define CONFIG_SYS_PROMPT "U-Boot # "
216#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
217/* Print Buffer Size */
218#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
219 sizeof(CONFIG_SYS_PROMPT) + 16)
220#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
221/* Boot Argument Buffer Size */
222#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
223
224#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
225 /* works on */
226#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
227 0x01F00000) /* 31MB */
228
229#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
230 /* load address */
231
232#define CONFIG_SYS_MONITOR_LEN (256 << 10)
233
234/*
235 * OMAP3 has 12 GP timers, they can be driven by the system clock
236 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
237 * This rate is divided by a local divisor.
238 */
239#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
240#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
241#define CONFIG_SYS_HZ 1000
242
243/*
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400244 * Physical Memory Map
245 *
246 */
247#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
248#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400249#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
250
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400251/*
252 * FLASH and environment organization
253 */
254
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000255#ifdef CONFIG_BOOT_ONENAND
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400256#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
257
258#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
259
260#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
261
262#define CONFIG_ENV_IS_IN_ONENAND 1
263#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
264#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
Javier Martinez Canillasca511cf2012-07-28 01:19:32 +0000265#endif
266
267#ifdef CONFIG_BOOT_NAND
268#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
269#define CONFIG_NAND_OMAP_GPMC
270#define CONFIG_SYS_NAND_BASE NAND_BASE
271#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
272#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
273#define CONFIG_ENV_IS_IN_NAND 1
274#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
275#define CONFIG_ENV_ADDR NAND_ENV_OFFSET
276#define CONFIG_SYS_MAX_NAND_DEVICE 1
277#endif
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400278
279/*
280 * Size of malloc() pool
281 */
282#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400283
284/*
285 * SMSC911x Ethernet
286 */
287#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400288#define CONFIG_SMC911X
289#define CONFIG_SMC911X_32_BIT
290#define CONFIG_SMC911X_BASE 0x2C000000
291#endif /* (CONFIG_CMD_NET) */
292
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000293/*
294 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
295 * and older u-boot.bin with the new U-Boot SPL.
296 */
297#define CONFIG_SYS_TEXT_BASE 0x80008000
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400298#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Steve Sakoman31bfcf12010-10-27 05:04:30 -0700299#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
300#define CONFIG_SYS_INIT_RAM_SIZE 0x800
301#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
302 CONFIG_SYS_INIT_RAM_SIZE - \
303 GENERATED_GBL_DATA_SIZE)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400304
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000305/* SPL */
306#define CONFIG_SPL
Tom Rini47f7bca2012-08-13 12:03:19 -0700307#define CONFIG_SPL_FRAMEWORK
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000308#define CONFIG_SPL_NAND_SIMPLE
309#define CONFIG_SPL_TEXT_BASE 0x40200800
310#define CONFIG_SPL_MAX_SIZE (54 * 1024)
311#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
312
313/* move malloc and bss high to prevent clashing with the main image */
314#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
315#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
316#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
317#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
318
319/* MMC boot config */
320#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
321#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
322#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
323#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
324
Javier Martinez Canillas0e29a242012-12-28 02:51:53 +0000325#define CONFIG_SPL_BOARD_INIT
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000326#define CONFIG_SPL_LIBCOMMON_SUPPORT
327#define CONFIG_SPL_LIBDISK_SUPPORT
328#define CONFIG_SPL_I2C_SUPPORT
329#define CONFIG_SPL_LIBGENERIC_SUPPORT
330#define CONFIG_SPL_MMC_SUPPORT
331#define CONFIG_SPL_FAT_SUPPORT
332#define CONFIG_SPL_SERIAL_SUPPORT
333
334#define CONFIG_SPL_POWER_SUPPORT
335#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
336
337#ifdef CONFIG_BOOT_ONENAND
338#define CONFIG_SPL_ONENAND_SUPPORT
339
340/* OneNAND boot config */
341#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
342#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
343#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
344#define CONFIG_SPL_ONENAND_LOAD_SIZE \
345 (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
346
347#endif
348
349#ifdef CONFIG_BOOT_NAND
350#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500351#define CONFIG_SPL_NAND_BASE
352#define CONFIG_SPL_NAND_DRIVERS
353#define CONFIG_SPL_NAND_ECC
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000354
355/* NAND boot config */
356#define CONFIG_SYS_NAND_5_ADDR_CYCLE
357#define CONFIG_SYS_NAND_PAGE_COUNT 64
358#define CONFIG_SYS_NAND_PAGE_SIZE 2048
359#define CONFIG_SYS_NAND_OOBSIZE 64
360#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
361#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
362#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
363 10, 11, 12, 13}
364#define CONFIG_SYS_NAND_ECCSIZE 512
365#define CONFIG_SYS_NAND_ECCBYTES 3
366#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
367#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
368#endif
369
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +0000370#endif /* __IGEP00X0_H */