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Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02001/*
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +01002 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02003 * wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020011/*
12 * High Level Configuration Options
13 * (easy to change)
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010014 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010015#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
16#define CONFIG_V38B 1 /* ...on V38B board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020017
18#define CONFIG_SYS_TEXT_BASE 0xFF000000
19
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020021
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010022#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
23#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020024
Bartlomiej Siekace3f1a42006-11-11 22:48:22 +010025#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020026
27#define CONFIG_NETCONSOLE 1
28
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010029#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
Mike Frysingerd8d21e62009-02-16 18:03:14 -050030#define CONFIG_MISC_INIT_R
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020031
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020033
Becky Bruce31d82672008-05-08 19:02:12 -050034#define CONFIG_HIGH_BATS 1 /* High BATs supported */
35
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020036/*
37 * Serial console configuration
38 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010039#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020041
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020042/*
43 * DDR
44 */
45#define SDRAM_DDR 1 /* is DDR */
46/* Settings for XLB = 132 MHz */
47#define SDRAM_MODE 0x018D0000
48#define SDRAM_EMODE 0x40090000
49#define SDRAM_CONTROL 0x704f0f00
50#define SDRAM_CONFIG1 0x73722930
51#define SDRAM_CONFIG2 0x47770000
52#define SDRAM_TAPDELAY 0x10000000
53
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020054/*
Robert P. J. Day62a3b7d2016-07-15 13:44:45 -040055 * PCI - no support
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020056 */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020057
58/*
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020059 * USB
60 */
61#define CONFIG_USB_OHCI
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010062#define CONFIG_USB_CLOCK 0x0001BBBB
63#define CONFIG_USB_CONFIG 0x00001000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020064
65/*
Jon Loeliger079a1362007-07-10 10:12:10 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
Jon Loeliger079a1362007-07-10 10:12:10 -050073/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050074 * Command line configuration.
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020075 */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050076#define CONFIG_CMD_IDE
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050077#define CONFIG_CMD_IRQ
78#define CONFIG_CMD_JFFS2
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050079#define CONFIG_CMD_SDRAM
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050080
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010081#define CONFIG_TIMESTAMP /* Print image info with timestamp */
82
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020083/*
84 * Boot low with 16 MB Flash
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_LOWBOOT 1
87#define CONFIG_SYS_LOWBOOT16 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020088
89/*
90 * Autobooting
91 */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020092
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010093#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010094 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020095 "echo"
96
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010097#undef CONFIG_BOOTARGS
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020098
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +020099#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200100 "bootcmd=run net_nfs\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100101 "bootdelay=3\0" \
102 "baudrate=115200\0" \
103 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
104 "filesystem over NFS; echo\0" \
105 "netdev=eth0\0" \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100106 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200107 "addip=setenv bootargs $(bootargs) " \
108 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
109 "$(netmask):$(hostname):$(netdev):off panic=1\0" \
110 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
111 "flash_self=run ramargs addip;bootm $(kernel_addr) " \
112 "$(ramdisk_addr)\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100113 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200114 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100115 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100116 "hostname=v38b\0" \
Heiko Schocher48690d82010-07-20 17:45:02 +0200117 "ethact=FEC\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100118 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
119 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
120 "cp.b 200000 ff000000 $(filesize);" \
121 "prot on ff000000 ff03ffff\0" \
122 "load=tftp 200000 $(u-boot)\0" \
123 "netmask=255.255.0.0\0" \
124 "ipaddr=192.168.160.18\0" \
125 "serverip=192.168.1.1\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100126 "bootfile=/tftpboot/v38b/uImage\0" \
127 "u-boot=/tftpboot/v38b/u-boot.bin\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200128 ""
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200129
130#define CONFIG_BOOTCOMMAND "run net_nfs"
131
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200132/*
133 * IPB Bus clocking configuration.
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100136
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200137/*
138 * I2C configuration
139 */
140#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
142#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
143#define CONFIG_SYS_I2C_SLAVE 0x7F
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200144
145/*
146 * EEPROM configuration
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
149#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
150#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
151#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200152
153/*
154 * RTC configuration
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_I2C_RTC_ADDR 0x51
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200157
158/*
159 * Flash configuration - use CFI driver
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200162#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
164#define CONFIG_SYS_FLASH_BASE 0xFF000000
165#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
166#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
167#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */
168#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
169#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200170
171/*
172 * Environment settings
173 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200174#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200176#define CONFIG_ENV_SIZE 0x10000
177#define CONFIG_ENV_SECT_SIZE 0x10000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200178#define CONFIG_ENV_OVERWRITE 1
179
180/*
181 * Memory map
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MBAR 0xF0000000
184#define CONFIG_SYS_SDRAM_BASE 0x00000000
185#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200186
187/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200189#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200190
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200191#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200193
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200194#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
196# define CONFIG_SYS_RAMBOOT 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200197#endif
198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
200#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
201#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200202
203/*
204 * Ethernet configuration
205 */
206#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800207#define CONFIG_MPC5xxx_FEC_MII100
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200208#define CONFIG_PHY_ADDR 0x00
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200209#define CONFIG_MII 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200210
211/*
212 * GPIO configuration
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200215
216/*
217 * Miscellaneous configurable options
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500220#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200222#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200224#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
226#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
227#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
230#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500235#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500237#endif
238
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200239/*
240 * Various low-level settings
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
243#define CONFIG_SYS_HID0_FINAL HID0_ICE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
246#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
247#define CONFIG_SYS_BOOTCS_CFG 0x00047801
248#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
249#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_CS_BURST 0x00000000
252#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200255
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100256/*
257 * IDE/ATA (supports IDE harddisk)
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200258 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100259#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
260#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
261#undef CONFIG_IDE_LED /* LED for ide not supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200262
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100263#define CONFIG_IDE_RESET /* reset for ide supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200264#define CONFIG_IDE_PREINIT
265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
267#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200280
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100281/*
282 * Status LED
283 */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200286#ifndef __ASSEMBLY__
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200287typedef unsigned int led_id_t;
288
289#define __led_toggle(_msk) \
290 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200292 } while(0)
293
294#define __led_set(_msk, _st) \
295 do { \
296 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297 *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200298 else \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200300 } while(0)
301
302#define __led_init(_msk, st) \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100303 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100305 } while(0)
306#endif /* __ASSEMBLY__ */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200307
308#endif /* __CONFIG_H */