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Vasily Khoruzhickf19eb152016-03-20 18:37:00 -07001/*
2 * Aeronix Zipit Z2 configuration file
3 *
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
15#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16#define CONFIG_SYS_TEXT_BASE 0x0
17
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070018#undef CONFIG_SKIP_LOWLEVEL_INIT
19#define CONFIG_PREBOOT
20
21/*
22 * Environment settings
23 */
24#define CONFIG_ENV_OVERWRITE
25#define CONFIG_ENV_IS_IN_FLASH 1
26#define CONFIG_ENV_ADDR 0x40000
27#define CONFIG_ENV_SIZE 0x10000
28
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070029#define CONFIG_SYS_MALLOC_LEN (128*1024)
30#define CONFIG_ARCH_CPU_INIT
31
32#define CONFIG_BOOTCOMMAND \
33 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
34 "then " \
35 "source 0xa0000000; " \
36 "else " \
37 "bootm 0x50000; " \
38 "fi; "
39#define CONFIG_BOOTARGS \
40 "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
41#define CONFIG_TIMESTAMP
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070042#define CONFIG_CMDLINE_TAG
43#define CONFIG_SETUP_MEMORY_TAGS
44#define CONFIG_SYS_TEXT_BASE 0x0
45#define CONFIG_LZMA /* LZMA compression support */
46
47/*
48 * Serial Console Configuration
49 * STUART - the lower serial port on Colibri board
50 */
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070051#define CONFIG_STUART 1
52#define CONFIG_CONS_INDEX 2
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070053
54/*
55 * Bootloader Components Configuration
56 */
57#define CONFIG_CMD_ENV
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070058
59/*
60 * MMC Card Configuration
61 */
62#ifdef CONFIG_CMD_MMC
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070063#define CONFIG_PXA_MMC_GENERIC
64#define CONFIG_SYS_MMC_BASE 0xF0000000
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070065#endif
66
67/*
68 * SPI and LCD
69 */
70#ifdef CONFIG_CMD_SPI
71#define CONFIG_SOFT_SPI
Vasily Khoruzhick59fa0892016-03-20 18:37:01 -070072#define CONFIG_LCD_ROTATION
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070073#define CONFIG_PXA_LCD
74#define CONFIG_LMS283GF05
75
76#define SPI_DELAY udelay(10)
77#define SPI_SDA(val) zipitz2_spi_sda(val)
78#define SPI_SCL(val) zipitz2_spi_scl(val)
79#define SPI_READ zipitz2_spi_read()
80#ifndef __ASSEMBLY__
81void zipitz2_spi_sda(int);
82void zipitz2_spi_scl(int);
83unsigned char zipitz2_spi_read(void);
84#endif
85#endif
86
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070087#define CONFIG_SYS_LONGHELP /* undef to save memory */
88#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
89#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
90#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
91#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
92#define CONFIG_SYS_DEVICE_NULLDEV 1
93
94/*
95 * Clock Configuration
96 */
97#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
98
99/*
100 * SRAM Map
101 */
102#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
103#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
104
105/*
106 * DRAM Map
107 */
108#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
109#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
110#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
111
112#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
113#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
114
115#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
116#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
117
118#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
119
120#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
121#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
122
123/*
124 * NOR FLASH
125 */
126#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
127#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
128#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
129#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
130
131#define CONFIG_SYS_FLASH_CFI
132#define CONFIG_FLASH_CFI_DRIVER 1
133#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
134
135#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
136#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
137
138#define CONFIG_SYS_MAX_FLASH_BANKS 1
139#define CONFIG_SYS_MAX_FLASH_SECT 256
140
141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
142
143#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
144#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
145#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
146#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
147#define CONFIG_SYS_FLASH_PROTECTION
148
149/*
150 * GPIO settings
151 */
152#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
153#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
154#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
155#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
156#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
157#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
158#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
159#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
160#define CONFIG_SYS_GPCR0_VAL 0x00000000
161#define CONFIG_SYS_GPCR1_VAL 0x00000020
162#define CONFIG_SYS_GPCR2_VAL 0x00000000
163#define CONFIG_SYS_GPCR3_VAL 0x00000000
164#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
165#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
166#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
167#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
168#define CONFIG_SYS_GPSR0_VAL 0x06080400
169#define CONFIG_SYS_GPSR1_VAL 0x007f0000
170#define CONFIG_SYS_GPSR2_VAL 0x032a0000
171#define CONFIG_SYS_GPSR3_VAL 0x00000180
172
173#define CONFIG_SYS_PSSR_VAL 0x30
174
175/*
176 * Clock settings
177 */
178#define CONFIG_SYS_CKEN 0x00511220
179#define CONFIG_SYS_CCCR 0x00000190
180
181/*
182 * Memory settings
183 */
184#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
185#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
186#define CONFIG_SYS_MSC2_VAL 0x0000b884
187#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
188#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
189#define CONFIG_SYS_MDMRS_VAL 0x00000000
190#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
191#define CONFIG_SYS_SXCNFG_VAL 0x40044004
192
193/*
194 * PCMCIA and CF Interfaces
195 */
196#define CONFIG_SYS_MECR_VAL 0x00000001
197#define CONFIG_SYS_MCMEM0_VAL 0x00014307
198#define CONFIG_SYS_MCMEM1_VAL 0x00014307
199#define CONFIG_SYS_MCATT0_VAL 0x0001c787
200#define CONFIG_SYS_MCATT1_VAL 0x0001c787
201#define CONFIG_SYS_MCIO0_VAL 0x0001430f
202#define CONFIG_SYS_MCIO1_VAL 0x0001430f
203
204#include "pxa-common.h"
205
206#endif /* __CONFIG_H */