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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkfe8c2802002-11-03 00:38:21 +00002/*
3 * armboot - Startup Code for ARM920 CPU-core
4 *
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02005 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
6 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundel792a09e2009-05-13 10:54:10 +02007 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
wdenkfe8c2802002-11-03 00:38:21 +00008 */
9
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020010#include <asm-offsets.h>
Wolfgang Denk9689ddc2009-07-27 10:06:39 +020011#include <common.h>
wdenkfe8c2802002-11-03 00:38:21 +000012#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +000013
14/*
15 *************************************************************************
16 *
Peter Pearse80767a62007-09-05 16:04:41 +010017 * Startup Code (called from the ARM reset exception vector)
wdenkfe8c2802002-11-03 00:38:21 +000018 *
19 * do important init only if we don't start from memory!
20 * relocate armboot to ram
21 * setup stack
22 * jump to second stage
23 *
24 *************************************************************************
25 */
26
Albert ARIBAUD41623c92014-04-15 16:13:51 +020027 .globl reset
wdenkfe8c2802002-11-03 00:38:21 +000028
Albert ARIBAUD41623c92014-04-15 16:13:51 +020029reset:
Heiko Schochercc7cdcb2010-09-17 13:10:43 +020030 /*
31 * set the cpu to SVC32 mode
32 */
33 mrs r0, cpsr
34 bic r0, r0, #0x1f
35 orr r0, r0, #0xd3
36 msr cpsr, r0
37
Heiko Schochercc7cdcb2010-09-17 13:10:43 +020038 /*
39 * we do sys-critical inits only at reboot,
40 * not when booting from ram!
41 */
Tom Rinia2ac2b92021-08-27 21:18:30 -040042#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Heiko Schochercc7cdcb2010-09-17 13:10:43 +020043 bl cpu_init_crit
44#endif
45
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000046 bl _main
Heiko Schochercc7cdcb2010-09-17 13:10:43 +020047
48/*------------------------------------------------------------------------------*/
49
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000050 .globl c_runtime_cpu_setup
51c_runtime_cpu_setup:
52
53 mov pc, lr
54
wdenkfe8c2802002-11-03 00:38:21 +000055/*
56 *************************************************************************
57 *
58 * CPU_init_critical registers
59 *
60 * setup important registers
61 * setup memory timing
62 *
63 *************************************************************************
64 */
65
66
Tom Rinia2ac2b92021-08-27 21:18:30 -040067#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
wdenkfe8c2802002-11-03 00:38:21 +000068cpu_init_crit:
69 /*
70 * flush v4 I/D caches
71 */
72 mov r0, #0
73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
75
76 /*
77 * disable MMU stuff and caches
78 */
79 mrc p15, 0, r0, c1, c0, 0
80 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
81 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
Yuichiro Gotoba10b852016-02-25 10:23:34 +090082 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
wdenkfe8c2802002-11-03 00:38:21 +000083 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
84 mcr p15, 0, r0, c1, c0, 0
85
Tom Rinia2ac2b92021-08-27 21:18:30 -040086#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
wdenkfe8c2802002-11-03 00:38:21 +000087 /*
88 * before relocating, we have to setup RAM timing
89 * because memory timing is board-dependend, you will
wdenk400558b2005-04-02 23:52:25 +000090 * find a lowlevel_init.S in your board directory.
wdenkfe8c2802002-11-03 00:38:21 +000091 */
92 mov ip, lr
Peter Pearsed4fc6012007-08-14 10:10:52 +010093
wdenk400558b2005-04-02 23:52:25 +000094 bl lowlevel_init
wdenkfe8c2802002-11-03 00:38:21 +000095 mov lr, ip
Simon Glassb5bd0982016-05-05 07:28:06 -060096#endif
wdenkfe8c2802002-11-03 00:38:21 +000097 mov pc, lr
Tom Rinia2ac2b92021-08-27 21:18:30 -040098#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */