blob: 3d099b4f11f7bafcbdb5651f463660e036ec0bdc [file] [log] [blame]
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +09009#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
10
11/*
12 * SDRAM (for initialize)
13 */
14#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
15#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
16
17#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
18#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
19
20#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
21
22/*
23 * Boot info
24 */
25#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090026
27/*
28 * Hardware drivers support
29 */
30
31/* RTC */
32#define CONFIG_SYS_I2C_RTC_ADDR 0x51
33
34/* Serial (pl011) */
35#define UART_CLK (62500000)
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090036#define CONFIG_PL011_CLOCK UART_CLK
37#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
38
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090039/* Support MTD */
40#define CONFIG_SYS_MAX_FLASH_BANKS 1
41#define CONFIG_SYS_FLASH_BASE (0x08000000)
42#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
43
44#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
45#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
46
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090047#define CONFIG_SYS_CBSIZE 1024
48#define CONFIG_SYS_MAXARGS 128
49#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
50
51/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
52/* #define CONFIG_SYS_PCI_64BIT 1 */
53
Masami Hiramatsu3a373862021-06-04 18:45:31 +090054#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
Masami Hiramatsu4d492b02021-11-10 09:40:07 +090055 "mtd nor1=u-boot.bin raw 200000 100000;" \
Masami Hiramatsu3a373862021-06-04 18:45:31 +090056 "fip.bin raw 180000 78000;" \
57 "optee.bin raw 500000 100000\0"
58
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090059/* Distro boot settings */
60#ifndef CONFIG_SPL_BUILD
61#ifdef CONFIG_CMD_USB
62#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
63#else
64#define BOOT_TARGET_DEVICE_USB(func)
65#endif
66
67#ifdef CONFIG_CMD_MMC
68#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
69#else
70#define BOOT_TARGET_DEVICE_MMC(func)
71#endif
72
73#ifdef CONFIG_CMD_NVME
74#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
75#else
76#define BOOT_TARGET_DEVICE_NVME(func)
77#endif
78
79#ifdef CONFIG_CMD_SCSI
80#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
81#else
82#define BOOT_TARGET_DEVICE_SCSI(func)
83#endif
84
85#define BOOT_TARGET_DEVICES(func) \
86 BOOT_TARGET_DEVICE_USB(func) \
87 BOOT_TARGET_DEVICE_MMC(func) \
88 BOOT_TARGET_DEVICE_SCSI(func) \
89 BOOT_TARGET_DEVICE_NVME(func) \
90
91#include <config_distro_bootcmd.h>
92#else /* CONFIG_SPL_BUILD */
93#define BOOTENV
94#endif
95
96#define CONFIG_EXTRA_ENV_SETTINGS \
97 "fdt_addr_r=0x9fe00000\0" \
98 "kernel_addr_r=0x90000000\0" \
99 "ramdisk_addr_r=0xa0000000\0" \
100 "scriptaddr=0x88000000\0" \
101 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu3a373862021-06-04 18:45:31 +0900102 DEFAULT_DFU_ALT_INFO \
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +0900103 BOOTENV
104
105#endif /* __CONFIG_H */