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wdenkd126bfb2003-04-10 11:18:18 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkd126bfb2003-04-10 11:18:18 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1
37#define CONFIG_MPC860T 1
38#define CONFIG_MPC862 1
39
40#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
41
42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43#undef CONFIG_8xx_CONS_SMC2
44#undef CONFIG_8xx_CONS_NONE
45
46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
47
wdenkae3af052003-08-07 22:18:11 +000048#define CONFIG_BOOTCOUNT_LIMIT
wdenkd126bfb2003-04-10 11:18:18 +000049
wdenkae3af052003-08-07 22:18:11 +000050#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkd126bfb2003-04-10 11:18:18 +000051
52#define CONFIG_BOARD_TYPES 1 /* support board types */
53
54#define CONFIG_PREBOOT "echo;" \
55 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
56 "echo"
57
58#undef CONFIG_BOOTARGS
59
60#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000061 "netdev=eth0\0" \
wdenkd126bfb2003-04-10 11:18:18 +000062 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd126bfb2003-04-10 11:18:18 +000064 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd126bfb2003-04-10 11:18:18 +000068 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "bootm ${kernel_addr}\0" \
wdenkd126bfb2003-04-10 11:18:18 +000070 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd126bfb2003-04-10 11:18:18 +000073 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenk5e4be002004-01-31 20:13:31 +000074 "bootfile=/tftpboot/TQM862L/uImage\0" \
wdenkd126bfb2003-04-10 11:18:18 +000075 "kernel_addr=40040000\0" \
76 "ramdisk_addr=40100000\0" \
77 ""
78#define CONFIG_BOOTCOMMAND "run flash_self"
79
80#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
81#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
82
83#undef CONFIG_WATCHDOG /* watchdog disabled */
84
85#define CONFIG_STATUS_LED 1 /* Status LED enabled */
86
87#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
88
Jon Loeliger37d4bb72007-07-09 21:38:02 -050089/*
90 * BOOTP options
91 */
92#define CONFIG_BOOTP_SUBNETMASK
93#define CONFIG_BOOTP_GATEWAY
94#define CONFIG_BOOTP_HOSTNAME
95#define CONFIG_BOOTP_BOOTPATH
96#define CONFIG_BOOTP_BOOTFILESIZE
97
wdenkd126bfb2003-04-10 11:18:18 +000098
99#define CONFIG_MAC_PARTITION
100#define CONFIG_DOS_PARTITION
101
102#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
103
wdenkd126bfb2003-04-10 11:18:18 +0000104
Jon Loeliger26946902007-07-04 22:30:50 -0500105/*
106 * Command line configuration.
107 */
108#include <config_cmd_default.h>
109
110#define CONFIG_CMD_ASKENV
111#define CONFIG_CMD_DATE
112#define CONFIG_CMD_DHCP
113#define CONFIG_CMD_IDE
114#define CONFIG_CMD_NFS
115#define CONFIG_CMD_SNTP
116
wdenkd126bfb2003-04-10 11:18:18 +0000117
118/*
119 * Miscellaneous configurable options
120 */
121#define CFG_LONGHELP /* undef to save memory */
122#define CFG_PROMPT "=> " /* Monitor Command Prompt */
123
Wolfgang Denk2751a952006-10-28 02:29:14 +0200124#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
125#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkd126bfb2003-04-10 11:18:18 +0000126#ifdef CFG_HUSH_PARSER
127#define CFG_PROMPT_HUSH_PS2 "> "
128#endif
129
Jon Loeliger26946902007-07-04 22:30:50 -0500130#if defined(CONFIG_CMD_KGDB)
wdenkd126bfb2003-04-10 11:18:18 +0000131#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
132#else
133#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
134#endif
135#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
136#define CFG_MAXARGS 16 /* max number of command args */
137#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
138
139#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
140#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
141
142#define CFG_LOAD_ADDR 0x100000 /* default load address */
143
144#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
145
146#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
147
148/*
149 * Low Level Configuration Settings
150 * (address mappings, register initial values, etc.)
151 * You should know what you are doing if you make changes here.
152 */
153/*-----------------------------------------------------------------------
154 * Internal Memory Mapped Register
155 */
156#define CFG_IMMR 0xFFF00000
157
158/*-----------------------------------------------------------------------
159 * Definitions for initial stack pointer and data area (in DPRAM)
160 */
161#define CFG_INIT_RAM_ADDR CFG_IMMR
162#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
163#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
164#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
165#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
166
167/*-----------------------------------------------------------------------
168 * Start addresses for the final memory configuration
169 * (Set up by the startup code)
170 * Please note that CFG_SDRAM_BASE _must_ start at 0
171 */
172#define CFG_SDRAM_BASE 0x00000000
173#define CFG_FLASH_BASE 0x40000000
174#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
175#define CFG_MONITOR_BASE CFG_FLASH_BASE
176#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
177
178/*
179 * For booting Linux, the board info and command line data
180 * have to be in the first 8 MB of memory, since this is
181 * the maximum mapped by the Linux kernel during initialization.
182 */
183#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
184
185/*-----------------------------------------------------------------------
186 * FLASH organization
187 */
188#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
189#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
190
191#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
192#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
193
194#define CFG_ENV_IS_IN_FLASH 1
wdenk71f95112003-06-15 22:40:42 +0000195
wdenkd126bfb2003-04-10 11:18:18 +0000196#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
197#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
198
199/* Address and size of Redundant Environment Sector */
200#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
201#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
202
203/*-----------------------------------------------------------------------
204 * Hardware Information Block
205 */
206#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
207#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
208#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
209
210/*-----------------------------------------------------------------------
211 * Cache Configuration
212 */
213#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500214#if defined(CONFIG_CMD_KGDB)
wdenkd126bfb2003-04-10 11:18:18 +0000215#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
216#endif
217
218/*-----------------------------------------------------------------------
219 * SYPCR - System Protection Control 11-9
220 * SYPCR can only be written once after reset!
221 *-----------------------------------------------------------------------
222 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
223 */
224#if defined(CONFIG_WATCHDOG)
225#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
226 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
227#else
228#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
229#endif
230
231/*-----------------------------------------------------------------------
232 * SIUMCR - SIU Module Configuration 11-6
233 *-----------------------------------------------------------------------
234 * PCMCIA config., multi-function pin tri-state
235 */
236#ifndef CONFIG_CAN_DRIVER
237#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
238#else /* we must activate GPL5 in the SIUMCR for CAN */
239#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
240#endif /* CONFIG_CAN_DRIVER */
241
242/*-----------------------------------------------------------------------
243 * TBSCR - Time Base Status and Control 11-26
244 *-----------------------------------------------------------------------
245 * Clear Reference Interrupt Status, Timebase freezing enabled
246 */
247#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
248
249/*-----------------------------------------------------------------------
250 * RTCSC - Real-Time Clock Status and Control Register 11-27
251 *-----------------------------------------------------------------------
252 */
253#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
254
255/*-----------------------------------------------------------------------
256 * PISCR - Periodic Interrupt Status and Control 11-31
257 *-----------------------------------------------------------------------
258 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
259 */
260#define CFG_PISCR (PISCR_PS | PISCR_PITF)
261
262/*-----------------------------------------------------------------------
263 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
264 *-----------------------------------------------------------------------
265 * Reset PLL lock status sticky bit, timer expired status bit and timer
266 * interrupt status bit
wdenkd126bfb2003-04-10 11:18:18 +0000267 */
wdenkd126bfb2003-04-10 11:18:18 +0000268#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkd126bfb2003-04-10 11:18:18 +0000269
270/*-----------------------------------------------------------------------
271 * SCCR - System Clock and reset Control Register 15-27
272 *-----------------------------------------------------------------------
273 * Set clock output, timebase and RTC source and divider,
274 * power management and some other internal clocks
275 */
276#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000277#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd126bfb2003-04-10 11:18:18 +0000278 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
279 SCCR_DFALCD00)
wdenkd126bfb2003-04-10 11:18:18 +0000280
281/*-----------------------------------------------------------------------
282 * PCMCIA stuff
283 *-----------------------------------------------------------------------
284 *
285 */
286#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
287#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
288#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
289#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
290#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
291#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
292#define CFG_PCMCIA_IO_ADDR (0xEC000000)
293#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
294
295/*-----------------------------------------------------------------------
296 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
297 *-----------------------------------------------------------------------
298 */
299
300#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
301
302#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
303#undef CONFIG_IDE_LED /* LED for ide not supported */
304#undef CONFIG_IDE_RESET /* reset for ide not supported */
305
306#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
307#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
308
309#define CFG_ATA_IDE0_OFFSET 0x0000
310
311#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
312
313/* Offset for data I/O */
314#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
315
316/* Offset for normal register accesses */
317#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
318
319/* Offset for alternate registers */
320#define CFG_ATA_ALT_OFFSET 0x0100
321
322/*-----------------------------------------------------------------------
323 *
324 *-----------------------------------------------------------------------
325 *
326 */
wdenkd126bfb2003-04-10 11:18:18 +0000327#define CFG_DER 0
328
329/*
330 * Init Memory Controller:
331 *
332 * BR0/1 and OR0/1 (FLASH)
333 */
334
335#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
wdenk71f95112003-06-15 22:40:42 +0000336#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
wdenkd126bfb2003-04-10 11:18:18 +0000337
338/* used to re-map FLASH both when starting from SRAM or FLASH:
339 * restrict access enough to keep SRAM working (if any)
340 * but not too much to meddle with FLASH accesses
341 */
342#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
343#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
344
345/*
346 * FLASH timing:
347 */
wdenkd126bfb2003-04-10 11:18:18 +0000348#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
349 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkd126bfb2003-04-10 11:18:18 +0000350
351#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
352#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
353#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
354
355#define CFG_OR1_REMAP CFG_OR0_REMAP
356#define CFG_OR1_PRELIM CFG_OR0_PRELIM
357#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
358
359/*
360 * BR2/3 and OR2/3 (SDRAM)
361 *
362 */
363#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
364#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
365#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
366
367/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
368#define CFG_OR_TIMING_SDRAM 0x00000A00
369
370#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
371#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
372
373#ifndef CONFIG_CAN_DRIVER
374#define CFG_OR3_PRELIM CFG_OR2_PRELIM
375#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
376#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
377#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
378#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
379#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
380#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
381 BR_PS_8 | BR_MS_UPMB | BR_V )
382#endif /* CONFIG_CAN_DRIVER */
383
384/*
385 * Memory Periodic Timer Prescaler
386 *
387 * The Divider for PTA (refresh timer) configuration is based on an
388 * example SDRAM configuration (64 MBit, one bank). The adjustment to
389 * the number of chip selects (NCS) and the actually needed refresh
390 * rate is done by setting MPTPR.
391 *
392 * PTA is calculated from
393 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
394 *
395 * gclk CPU clock (not bus clock!)
396 * Trefresh Refresh cycle * 4 (four word bursts used)
397 *
398 * 4096 Rows from SDRAM example configuration
399 * 1000 factor s -> ms
400 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
401 * 4 Number of refresh cycles per period
402 * 64 Refresh cycle in ms per number of rows
403 * --------------------------------------------
404 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
405 *
wdenk73a8b272003-06-05 19:27:42 +0000406 * 50 MHz => 50.000.000 / Divider = 98
407 * 66 Mhz => 66.000.000 / Divider = 129
408 * 80 Mhz => 80.000.000 / Divider = 156
409 * 100 Mhz => 100.000.000 / Divider = 195
wdenkd126bfb2003-04-10 11:18:18 +0000410 */
wdenke9132ea2004-04-24 23:23:30 +0000411
412#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
413#define CFG_MAMR_PTA 98
wdenkd126bfb2003-04-10 11:18:18 +0000414
415/*
416 * For 16 MBit, refresh rates could be 31.3 us
417 * (= 64 ms / 2K = 125 / quad bursts).
418 * For a simpler initialization, 15.6 us is used instead.
419 *
420 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
421 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
422 */
423#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
424#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
425
426/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
427#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
428#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
429
430/*
431 * MAMR settings for SDRAM
432 */
433
434/* 8 column SDRAM */
435#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
436 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
437 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
438/* 9 column SDRAM */
439#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
440 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
441 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
442
443
444/*
445 * Internal Definitions
446 *
447 * Boot Flags
448 */
449#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
450#define BOOTFLAG_WARM 0x02 /* Software reboot */
451
452#define CONFIG_NET_MULTI
453#define CONFIG_SCC1_ENET
454#define CONFIG_FEC_ENET
455#define CONFIG_ETHPRIME "SCC ETHERNET"
456
457#endif /* __CONFIG_H */