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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
26 * U-Boot port on RPXlite board
27 *
28 * DRAM related UPMA register values are modified.
29 * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
30 */
31
32#include <common.h>
33#include <mpc8xx.h>
34
35/* ------------------------------------------------------------------------- */
36
37static long int dram_size (long int, long int *, long int);
38
39/* ------------------------------------------------------------------------- */
40
41#define _NOT_USED_ 0xFFFFCC25
42
wdenkc83bf6a2004-01-06 22:38:14 +000043const uint sdram_table[] = {
wdenk5b1d7132002-11-03 00:07:02 +000044 /*
45 * Single Read. (Offset 00h in UPMA RAM)
46 */
47 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
wdenkc83bf6a2004-01-06 22:38:14 +000048 0x3FBFCC27, /* last */
wdenk5b1d7132002-11-03 00:07:02 +000049 _NOT_USED_, _NOT_USED_, _NOT_USED_,
50
51 /*
52 * Burst Read. (Offset 08h in UPMA RAM)
53 */
54 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
wdenkc83bf6a2004-01-06 22:38:14 +000055 0x3FBFCC27, /* last */
wdenk5b1d7132002-11-03 00:07:02 +000056 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 _NOT_USED_, _NOT_USED_, _NOT_USED_,
59
60 /*
61 * Single Write. (Offset 18h in UPMA RAM)
62 */
63 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
wdenkc83bf6a2004-01-06 22:38:14 +000064 0x3FFFCC27, /* last */
wdenk5b1d7132002-11-03 00:07:02 +000065 _NOT_USED_, _NOT_USED_, _NOT_USED_,
66
67 /*
68 * Burst Write. (Offset 20h in UPMA RAM)
69 */
70 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
wdenkc83bf6a2004-01-06 22:38:14 +000071 0x0CFFCC00, 0x33FFCC27, /* last */
wdenk5b1d7132002-11-03 00:07:02 +000072 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_,
75
76 /*
77 * Refresh. (Offset 30h in UPMA RAM)
78 */
79 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
wdenkc83bf6a2004-01-06 22:38:14 +000080 0x3FFFCC27, /* last */
wdenk5b1d7132002-11-03 00:07:02 +000081 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_,
83
84 /*
85 * Exception. (Offset 3Ch in UPMA RAM)
86 */
87 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
88};
89
90/* ------------------------------------------------------------------------- */
91
92
93/*
94 * Check Board Identity:
95 */
96
97int checkboard (void)
98{
wdenkc83bf6a2004-01-06 22:38:14 +000099 puts ("Board: RPXlite\n");
100 return (0);
wdenk5b1d7132002-11-03 00:07:02 +0000101}
102
103/* ------------------------------------------------------------------------- */
104
Becky Bruce9973e3c2008-06-09 16:03:40 -0500105phys_size_t initdram (int board_type)
wdenk5b1d7132002-11-03 00:07:02 +0000106{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc83bf6a2004-01-06 22:38:14 +0000108 volatile memctl8xx_t *memctl = &immap->im_memctl;
109 long int size10;
wdenk5b1d7132002-11-03 00:07:02 +0000110
wdenkc83bf6a2004-01-06 22:38:14 +0000111 upmconfig (UPMA, (uint *) sdram_table,
112 sizeof (sdram_table) / sizeof (uint));
wdenk5b1d7132002-11-03 00:07:02 +0000113
114 /* Refresh clock prescalar */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenk5b1d7132002-11-03 00:07:02 +0000116
wdenkc83bf6a2004-01-06 22:38:14 +0000117 memctl->memc_mar = 0x00000000;
wdenk5b1d7132002-11-03 00:07:02 +0000118
119 /* Map controller banks 1 to the SDRAM bank */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
121 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
wdenk5b1d7132002-11-03 00:07:02 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenk5b1d7132002-11-03 00:07:02 +0000124
wdenkc83bf6a2004-01-06 22:38:14 +0000125 udelay (200);
wdenk5b1d7132002-11-03 00:07:02 +0000126
wdenkc83bf6a2004-01-06 22:38:14 +0000127 /* perform SDRAM initializsation sequence */
wdenk5b1d7132002-11-03 00:07:02 +0000128
wdenkc83bf6a2004-01-06 22:38:14 +0000129 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
130 udelay (1);
wdenk5b1d7132002-11-03 00:07:02 +0000131
wdenkc83bf6a2004-01-06 22:38:14 +0000132 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
wdenk5b1d7132002-11-03 00:07:02 +0000133
wdenkc83bf6a2004-01-06 22:38:14 +0000134 udelay (1000);
wdenk5b1d7132002-11-03 00:07:02 +0000135
136 /* Check Bank 0 Memory Size
137 * try 10 column mode
138 */
139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
wdenkc83bf6a2004-01-06 22:38:14 +0000141 SDRAM_MAX_SIZE);
wdenk5b1d7132002-11-03 00:07:02 +0000142
wdenkc83bf6a2004-01-06 22:38:14 +0000143 return (size10);
wdenk5b1d7132002-11-03 00:07:02 +0000144}
145
146/* ------------------------------------------------------------------------- */
147
148/*
149 * Check memory range for valid RAM. A simple memory test determines
150 * the actually available RAM size between addresses `base' and
151 * `base + maxsize'. Some (not all) hardware errors are detected:
152 * - short between address lines
153 * - short between data lines
154 */
155
wdenkc83bf6a2004-01-06 22:38:14 +0000156static long int dram_size (long int mamr_value, long int *base,
157 long int maxsize)
wdenk5b1d7132002-11-03 00:07:02 +0000158{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc83bf6a2004-01-06 22:38:14 +0000160 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk5b1d7132002-11-03 00:07:02 +0000161
wdenkc83bf6a2004-01-06 22:38:14 +0000162 memctl->memc_mamr = mamr_value;
wdenk5b1d7132002-11-03 00:07:02 +0000163
wdenkc83bf6a2004-01-06 22:38:14 +0000164 return (get_ram_size (base, maxsize));
wdenk5b1d7132002-11-03 00:07:02 +0000165}